Fast direct gps signal acquisition using fpga
Download
1 / 23

Fast Direct GPS Signal Acquisition Using FPGA - PowerPoint PPT Presentation


  • 74 Views
  • Uploaded on

Fast Direct GPS Signal Acquisition Using FPGA. Jing Pang Janusz Starzyk. School of Electrical Engineering and Computer Science Ohio University Athens, OH U. S. A. Outline. Direct P-code Acquisition Overview GPS Background GPS signal structure

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about ' Fast Direct GPS Signal Acquisition Using FPGA' - kylie-adkins


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
Fast direct gps signal acquisition using fpga
Fast Direct GPS Signal Acquisition Using FPGA

Jing Pang

Janusz Starzyk

School of Electrical Engineering

and Computer Science

Ohio University

Athens, OH

U. S. A.

ECCTD’03


Outline
Outline

  • Direct P-code Acquisition Overview

  • GPS Background

    • GPS signal structure

    • Parallel code phase search for signal acquisition

  • P-code Generator Architecture

  • P-code Tuning Model

  • P-code Property

    • Noncircular convolution with zero padding

    • Autocorrelation and acquisition margin

  • Direct Average Method

  • Design Platform, Design Flow and Hardware Architecture

  • Summary

ECCTD’03


Direct p code acquisition
Direct P-code Acquisition

  • Time domain acquisition

    • Massive physical parallel correlators

  • FFT search

    • Most of the reported approaches require large size FFT

  • New approach

    • Direct average

    • Small size FFT for FPGA implementation

ECCTD’03


Gps signal structure

/2

L1 carrier

C/A code

Navigation message

P-code

L2 carrier

GPS Signal Structure

Modulo-2 summation

Mixer

Summation

ECCTD’03



Parallel code phase search
Parallel Code Phase Search

FFT-based Circular Correlator

Digital IF

Code Generator

Y

N

Carrier Generator

peak detected ?

more freq. bins ?

N

Y

Failed

Acquired

Acquisition Result

ECCTD’03


Circular correlator
Circular Correlator

AB*

ab

a

A

FFT

IFFT

b

B

B*

FFT

Conjugation

ECCTD’03


Gps p code generator
GPS P-code Generator

Short cycle:

4092, 4093

Held after

3749 short cycles

7 Day Reset

Extra 37 chips

Generate P-code

Different satellites

ECCTD’03


Lfsr x1 and x2
LFSR X1 And X2

X1B

X1A

X2B

X2A

ECCTD’03


Epochs
Epochs

ECCTD’03



P code generator tuning model
P-code Generator Tuning Model

z1a: index to the

X1A LFSR State at the specified Time

x1a: divide-by

3750 counter

y1a: z-counter value

ECCTD’03


P code property
P-code Property

  • Circular convolution for periodic code

  • Circular convolution with zero padding

ECCTD’03


P code property1
P-code Property

  • Each satellite uses unique P-code to implement CDMA technique

ECCTD’03


Acquisition margin
Acquisition Margin

  • Mean value of acquisition margin: 25.954

  • Standard deviation: 1.841

  • Each acquisition margin value is obtained over 1 ms

ECCTD’03


Direct average method
Direct Average Method

  • Direct average method is proposed due to the extremely long period of P-code

  • Direct average over 128 samples autocorrelation result

  • Summation of correlation results for 15 1-ms windows

ECCTD’03


Direct average method1
Direct Average Method

  • Acquisition margin distribution over 1 s.

  • The mean value of the acquisition margin: 26.882

  • The standard variation: 2.676

ECCTD’03


Design platform

VirtexE FPGA

Spartan PCI

Interface

Design Platform

  • Nallatech Board

PC’s PCI interface

ECCTD’03


Xilinx virtexe architecture
Xilinx VirtexE Architecture

  • Overall architecture

  • One Slice of a CLB

  • IOB

  • GRM

ECCTD’03


Design flow
Design Flow

Design Entry

Functional

Simulation

Timing

Simulation

User C++

Application

Design Synthesis

Nallatech DLL

Software Interface

Nallatech Custom

Hardware Interface

Mapping

Placement

Routing

VirtexE chip

Bit File

ECCTD’03


Fpga design partition
FPGA Design Partition

Average

IFFT Processor

FFT

Processor

GPS signal

Average

Local reference

generation unit

Local Reference FFT Processor

NCO

Maximum selection

Other control & decision logic

Correlation peak

& peak location

| |2

ECCTD’03


Virtexe fpga design cost
VirtexE FPGA Design Cost

1. NCO 2. P-code generator 3. Average 4. FFT 5. IFFT 6. Complex conjugate multiplication

7. Correlation amplitude square

8. Peak selection and decision logic

Total available CLB slices: 15552

Total available Block Rams: 144

ECCTD’03


Summary
Summary

  • Flexible GPS P-code generator tuning model

    • Produce P-code starting from any time of a GPS week

  • Direct Average Method

    • Improve acquisition speed

    • Simplify FPGA hardware design

  • Hardware FPGA implementation

ECCTD’03


ad