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Functional and Timing Abstraction

Functional and Timing Abstraction. Pirouz Bazargan Sabet. Patricia Renault. Dominique Le Dû. Outline. Functional Abstraction. Functional Abstraction. Delay Evaluation. Introduction. Layout. The input netlist contains : Transistors Capacitors Resistors. Extraction.

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Functional and Timing Abstraction

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  1. Functional and Timing Abstraction Pirouz Bazargan Sabet Patricia Renault Dominique Le Dû

  2. Outline Functional Abstraction Functional Abstraction Delay Evaluation

  3. Introduction Layout • The input netlist contains : • Transistors • Capacitors • Resistors Extraction Netlist Tr, C, R Abstraction Abstracted functional and timing view

  4. Functional Abstraction Aim : Recongnize gates from transistor network Pattern Matching Formal Method

  5. Functional Abstraction Classic Method : Pattern Matching pattern circuit

  6. Functional Abstraction Formal Method Recognize the function of a transistor structure Electrical point of view - Current trace

  7. a b a Fup = b + a b Fup = Fdown Functional Abstraction follow the current paths Fdown = a . b

  8. Fup = a.d + b.c Fup¹Fdown Fdown = a.c + b.d Ftri-state = Fup+Fdown = c.d.a.b+c.d.a.b Functional Abstraction c d b a b a Fconflict = Fup . Fdown = 0 d c

  9. x Fup = a.d + b.c Fup¹Fdown Fdown = a.c + b.d Ftri-state = Fup+Fdown = c.d.a.b+c.d.a.b Functional Abstraction a Fconflict = Fup . Fdown = 0 b = 0

  10. Functional Abstraction Formal Method : problems How far I have to explore ? Apparition of loops

  11. Functional Abstraction How far I have to explore ? - Recursive expansion

  12. Functional Abstraction How far I have to explore ? - Color simulation Minimal Supergate The graph may be incomplete

  13. Break point in the exploration Functional Abstraction Formal Method : Loops A loop is the signature of a memory point

  14. x Fup = a.d + b.c Fup=Fdown Fdown = a.c + b.d Functional Abstraction a b

  15. f = xi . fi1 + xi . fi0 Functional Abstraction Formal Method : Identifying a memory point for a memory point =fi1.fi0 ¹ 0 =fi1.fi0 º 0

  16. Functional Abstraction Formal Method : Identifying a memory point Formal analysis cannot identify memory points that are based on electrical conflicts Assume a correct design

  17. Functional Abstraction Formal Method Sort the potential gates (# of trs, pass trs) Build a gate (list of branches) Dual ? If not dual : Color simulation Analyze each branch Analyze the conflict and tri-state cond If dual : Loop analysis

  18. Outline Functional Abstraction Delay Evaluation Delay Evaluation

  19. Delay Evaluation How to characterize the delay of a transition

  20. y xi Delay Evaluation Accurate delay using electrical simulation Electrical simulation (Spice) of each configuration

  21. x a b Delay Evaluation Problem : Delay is environment dependent Analyze a group of gates

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