Coe4oi5 engineering design
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COE4OI5 Engineering Design. Chapter 2: UP2/UP3 board. UP3. UP3 board contains a Cyclone FPGA, several memory devices and a wide range of I/O features Two versions of the board are available one based on C6 and the other one based on C12 FPGA.

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COE4OI5 Engineering Design

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Coe4oi5 engineering design

COE4OI5Engineering Design

Chapter 2: UP2/UP3 board


Coe4oi5 engineering design

UP3

  • UP3 board contains a Cyclone FPGA, several memory devices and a wide range of I/O features

  • Two versions of the board are available one based on C6 and the other one based on C12 FPGA.

  • The FPGA and memory devices can be programmed using a JTAG ByteBlaster II cable attached to the PC printer (parallel) port

  • The printer port mode of the PC should be set in the PC’s BIOS to ECP or EPP.


Coe4oi5 engineering design

UP3

  • An on-board clock oscillator and clock chip provides several clock signals that are selectable with the board’s jumpers


Figure 2 1 the altera up 3 board

Figure 2.1 The Altera UP 3 board.


Figure 2 2 the altera up 3 board s features

Figure 2.2 The Altera UP 3 board’s features.


Coe4oi5 engineering design

Table 2.1 UP 3 Board’s Cyclone FPGA Features


Memory

Memory

  • In addition to the Cyclone FPGA’s internal memory, the UP3 has several external ROM and RAM memory

  • Capacities of external memories are much larger than internal memory but they have a longer access time

  • FPGA processor cores (e.g., Nios) use external memory for program and data memory and the FPGA’s internal memory for registers and cache

  • The serial flash chip is used to automatically load the FPGA’s serial configuration data at the power up in systems where you do not want to download the configuration data through the Byteblaster.


Coe4oi5 engineering design

Table 2.2 UP 3 Board’s Memory Features


Coe4oi5 engineering design

I/O

  • For most I/O devices, the UP3 board’s hardware provides only an electrical interface to the FPGA’s I/O pins

  • Logic that provides a device interface circuit or controller will need to be constructed using the FPGA’s internal logic (UP core functions)

  • Also remember to assign pins as shown in the tutorial to avoid turning on several of the memory devices at the same time

  • Do NOT connect high current devices such as motors or relay coils directly to FPGA I/O pins


Coe4oi5 engineering design

Table 2.3 Overview of the UP 3 Board’s I/O Features


Coe4oi5 engineering design

Table 2.4 UP 3 Board’s most commonly used FPGA I/O pin names and assignments


Coe4oi5 engineering design

Table 2.4 (continued) UP 3 Board’s most commonly used FPGA I/O pin names and assignments


Up2 max

UP2/MAX

  • UP2 board supports both a MAX and a FLEX device.

  • The devices can be programmed using a JTAG ByteBlaster II cable attached to the PC printer (parallel) port

  • Jumpers on the board select which device is programmed.

  • The MAX device is connected to two seven segment LED displays, two eight-position DIP switches, sixteen LEDs

  • Two push buttons can be connected to the MAX using jumper wires

  • Circuit board holes are provided for an additional 60-pin expansion header that can be added to connect external hardware


Coe4oi5 engineering design

Figures 2.1 and 2.2 The Altera UP 1 board.


Coe4oi5 engineering design

Table 2.1 UP 1 device selection jumpers for programming.


Up2 flex

UP2/FLEX

  • FLEX device is attached to a VGA connector, a PS/2 mouse and keyboard port, two seven segment displays, an eight-position DIP switch and two push buttons.

  • To generate video output, mouse or keyboard input, an interface must be designed using logic inside the FLEX device (UP core functions)

  • Circuit board holes are provided for three 60-pin expansion header that can be added to connect external hardware

  • Do NOT connect high current devices such as motors or relay coils directly to FPGA I/O pins


Coe4oi5 engineering design

Table 2.4 UP 1 Board 10K20RC240 FLEX CHIP I/O pin assignments.


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