1 / 10

A/D Converter Datapaths

A/D Converter Datapaths. Discussion D8.4. Analog-to-Digital Converters. Converts analog signals to digital signals 8-bit: 0 – 255 10-bit: 0 – 1023 12-bit: 0 – 4095 Successive Approximation. Method of Successive Approximation. Implementing Successive Approximation.

kolina
Download Presentation

A/D Converter Datapaths

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. A/D Converter Datapaths Discussion D8.4

  2. Analog-to-Digital Converters • Converts analog signals to digital signals • 8-bit: 0 – 255 • 10-bit: 0 – 1023 • 12-bit: 0 – 4095 • Successive Approximation

  3. Method of Successive Approximation

  4. Implementing Successive Approximation

  5. Implementing Successive Approximation

  6. A/D CPLD

  7. A/D CPLD Datapath

  8. A/D Datapath B SAR mask 1000 1100 1110 1111 1111 1000 0100 0010 0001 0000 0000 1000 1100 1110 1111

  9. module maskReg(clk,reset,sh,Q); input clk; input reset,sh; output [3:0] Q; reg [3:0] Q; // 4-bit Shift Register always @(posedge clk orposedge reset) begin if(reset == 1) Q <= 4'b1000; else begin if(sh == 1) begin Q[3] <= 0; Q[2:0] <= Q[3:1]; end end end endmodule maskR 0000 1000 0100 0010 0001 0000

  10. // Title: A/D converter datapath module ADpath(clk,reset,msel,sh,sarld,adld,sar,ADR,done); input clk,reset,msel,sh,sarld,adld; output done; output [3:0] sar,ADR; wire [3:0] sar,sarin,ADR,A,B; wire [3:0] mask; assign done = ~|mask; assign A = sar | mask; assign B = sar & ~mask; reg4 sarReg(.D(sarin),.Load(sarld),.Clear(reset),.Clk(clk), .Q(sar)); reg4 adReg(.D(sar),.Load(adld),.Clear(reset),.Clk(clk), .Q(ADR)); maskReg maskR(.clk(clk),.reset(reset),.sh(sh),.Q(mask)); mux24 mux1(.A(A),.B(B),.s(msel),.Y(sarin)); endmodule

More Related