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Accellera Systems Initiative Overview

Accellera Systems Initiative Overview. Bill Read | August, 2012. Our Mission. To provide design and verification standards required by systems, semiconductor, IP and design tool companies to enhance a front-end design automation process .

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Accellera Systems Initiative Overview

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  1. Accellera Systems Initiative Overview Bill Read | August, 2012

  2. Our Mission • To provide design and verification standards required by systems, semiconductor, IP and design tool companies to enhance a front-end design automation process. • To collaborate with its community of companies, individuals and organizations in delivering the standards that lower the cost to design commercial EDA, IC and embedded system solutions. Accellera Systems Initiative 2

  3. Broad Industry Support Associate Members Corporate Members • Diverse Membership from EDA Vendors, IP Suppliers, Semiconductor Manufacturers and System Houses 3

  4. Why Standards? 4 • Design tools & methodologies continue to evolve rapidly • Simulation • Emulation • IP integration • DFx Architecting DFx • Mixed environment • Standards help reduce overcall cost of migrating design, IP & tools

  5. Accellera Systems Initiative Board of Directors ShishpalRawat, Intel Marketing Committee • Thomas Li, Springsoft Technical Committee Karen Pieper, Tabula Administration • Interface (ITC)‏ • Brian Bailey • EDA DesignLine • Verilog-AMS • Scott Little • Intel • OVL • Kenneth Larson • Mentor Graphics • UCIS • Richard Ho • DE Shaw • SystemC • Synthesis • Andres Takach Calypto • SystemCLanguage • David Black Doulos • VIP • Hillel Miller Freescale • Tom Alsop Intel • IP Tagging • Kathy Werner • Freescale • SystemRDL • Oren Katzir • Intel • IP-XACT • Christian Fraisse • STMicrosystems • SystemC TLM • Bart VanthournoutSynopsys • SystemC AMS • Martin Barnasconi • NXP • SystemC CCI • Trevor WiemanIntel Supported IEEE Working Groups 1666 SystemC Stan Krolikoski Cadence • 1800 SystemVerilog • Karen Pieper • Tabula 1076 VHDL Jim Lewis SynthWorks 1801 UPF John Biggs ARM 5

  6. Accellera Standards Success Merger with SPIRIT Corporate IEEE Member IEEE IPR adopted Merger with OSCI Accellera formed from VI & OVI 2012 2011 2004 2010 2009 2008 2007 2002 2005 2003 2001 2006 2000 6

  7. OSCI Standards Success Merger with Accellera IEEE1666-2005 released OSCI formed OSCI 10 year anniversary IEEE1666- 2011 1999 2003 2005 2011 2010 2009 2006 2007 2004 2002 2000 2008 2001 2012 7

  8. Synergies and Future Opportunities • UVM, TLM-2.0, CCI • SystemC and UCIS • UVM and IP-XACT • SystemC and IP-XACT • System-Level Verification System-Level IP Integration • Mixed-Signal Design & Verification • Verilog-AMS, SystemVerilog AMS, SystemC AMS 8

  9. EDA and IP Design Standards and Initiatives SoCIntegration IP-XACT IP-Tagging UCIS SystemC System-Verilog Testbench UVM SCE-MI OVL SV-AMS UPF SDF OCI VHDL Verilog Design 9

  10. Ongoing Technical Activities Current Standards • Verification Intellectual Property (VIP) Universal Verification Methodology (UVM) 1.1 • Open Verification Library (OVL) 2.6 • Verilog-AMS (V-AMS) 2.3.1 • Standard Co-Emulation Modeling Interface (SCE-MI) 2.1 • Unified Coverage Interoperability Standard (UCIS) 1.0 • IP-XACT - Update to IEEE 1685 • Intellectual Property (IP) Tagging • SystemC Synthesizable Subset Draft 1.3 • SystemC Analog Mixed-Signal (AMS) 1.0 • SystemC Configuration, Control & Inspection (CCIRequirements) • SystemC Language Standard • SystemRDL (launched) • Transaction Level Modeling (TLM) 1.0 and 2.0 • Open Source Companions: • - UVM Reference Implementation 1.1 • - SystemC Proof of Concept Library (POCL) • - SystemCVerification Library 1.0p2 10th Annual DVCon – Our flagship conference 10

  11. Strong Relationship with IEEE • Using Get IEEE program to allow access to EDA standards • IEEE 1666 SystemC • IEEE 1685 IP-XACT • Accellera Systems Initiative Continues IEEE Standards Association Advanced Corporate Membership • 1076 VHDL • 1666 SystemC Language • 1685 IP-XACT • 1800 SystemVerilog (SV) • 1801 Unified Power Format (UPF)‏ • 1850 Property Specification Language (PSL)‏ 11

  12. What’s Next? Universal Verification Methodology (UVM) 2.0 Verilog and SystemC Analog/Mixed-Signal (AMS) SystemC Configuration, Control, & Inspection (CCI) IP Tagging IP-XACT SystemRDL 12

  13. Global Events 2013 • Silicon Valley: DVCon 2013 and North American SystemC Users Group Meeting • Germany: DATE 2013 and European SystemC Users Group Meeting • Bangalore: India SystemC Users Group Meeting, Spring 2013 • Austin, TX: DAC 2013 • Japan SystemC Users Group, July 2013 • Taiwan SystemC Users Group, Fall 2013 13

  14. Summary • Accellera Systems Initiative is the standards body for front-end design and IP integration • Ongoing Integration of Accellera and OSCI • Strong collaborative relationship With the IEEE A robust organization serving the electronics industry since 1987! www.accellera.org 14

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  16. Acronyms & Definitions AMS: Analog/Mixed Signal CCI: Configuration, Control & Inspection DVCon: Design & Verification Conference EDA: Electronic Design Automation GET: Free IEEE LRM download program IC: Integrated Circuit IP: Intellectual Property IPR: Intellectual Property Rights IP-XACT: Metadata standard for IP integration IEEE: Institute of Electrical and Electronics Engineers ITC: Interface Technical Committee LWG: Language Working Group OCI: Open Compression Interface OSCI: Open SystemC Initiative OVI: Open Verilog International OVL: Open Verification Library PSL: Property Specification Language SDF: Standard Delay Format SC: SystemC SCV: SystemC Verification SPIRIT: Structure for Packaging, Integrating, and Reusing IP within Tool-flows SV: SystemVerilog SWG: Synthesis Working Group TLM: Transaction-Level Modeling UCIS: Unified Coverage Interoperability Standard UPF: Unified Power Format UVM: Universal Verification Methodology V-AMS: Verilog-Analog/Mixed Signal VHDL: VHSIC Hardware Description Language VI: VHDL International VIP: Verification Intellectual Property 16

  17. Recent Accomplishments • Completed the merger to form the Accellera Systems Initiative • Hosted two SystemC User Group meetings in Taiwan • Held a session at IP-SOC in Grenoble, France about our EDA and IP Standards Roadmap • Published SystemC AMS extensions white paper • Completed next revision of the SystemC LRM, IEEE 1666-2011, which is available for free download • Continued interest in our IEEE 1685 (IP-XACT) standard with over 4000 free downloads to date • Released Video Tutorial "Software-Driven Verification Using TLM-2.0 Virtual Platforms“ • Released Unified Coverage Interoperability Standard (UCIS) 1.0 • Released the SystemC 2.3 Library • Accellera Systems Initiative Technical Achievement and Leadership Awards 17

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