Dynamic scheduling
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Δυναμική Δρομολόγηση Εντολών (Dynamic Scheduling) PowerPoint PPT Presentation


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Δυναμική Δρομολόγηση Εντολών (Dynamic Scheduling). Απόδοση pipeline. Pipeline CPI = Ideal pipeline CPI + Structural Stalls + Data Hazard Stalls + Control Stalls Ideal pipeline CPI : μέτρο της μέγιστης απόδοσης που μπορούμε να έχουμε με την εκάστοτε υλοποίηση του pipeline

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Δυναμική Δρομολόγηση Εντολών (Dynamic Scheduling)

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(Dynamic Scheduling)


pipeline

  • Pipeline CPI = Ideal pipeline CPI + Structural Stalls + Data Hazard Stalls + Control Stalls

    • Ideal pipeline CPI: pipeline

    • Structural hazards:

    • Data hazards: , pipeline

    • Control hazards: (branches,jumps)


CPI

Pipeline CPI =

Ideal pipeline CPI +

Structural Stalls +

Data Hazard Stalls +

Control Stalls

register renaming

loop unrolling

static scheduling, software pipelining

delayed branches, branch scheduling


Hazards

  • J data dependent I: H J source operand I

  • J data dependent , data dependent I ( )

  • (True Dependences)

  • Read After Write (RAW) hazards pipeline

I: add r1,r2,r3

J: sub r4,r1,r3


Hazards

  • hazard, hazard, , pipeline

    • 1) hazards

    • 2)

    • 3)


Name Dependences, (1): Anti-dependences

I: sub r4,r1,r3

J: add r1,r2,r3

K: mul r6,r1,r7

  • Name dependences: 2 (''name''),

  • Anti-dependence: J r1 I

  • Write After Read (WAR) hazards pipeline


Name Dependences, (2): Output dependences

I: sub r1,r4,r3

J: add r1,r2,r3

K: mul r6,r1,r7

  • Output dependence: J r1 I

  • Write After Write (WAW) hazards pipeline


ILP Data Hazards

  • : , , ,

  • HW/SW: ,


(1)

DIVD F0,F2,F4

ADDD F10,F0,F8

SUBD F12,F8,F14

  • dependence DIVD ADDD

  • dependence SUBD. ADDD?

  • Dynamic Scheduling: (out-of-order execution)

    • exceptions


(2)

  • compile time (.., )

  • compiler

  • , pipeline


(3)

    • in-order instruction issue

    • out-of-order execution

    • out-of-order completion

  • ID 5-stage pipeline 2

    • Issue: structural hazards (in order issue)

    • Read Operands: operands data hazards ( stall or bypass- - ooo execution)


execution

  • WAR WAW hazards

  • antidependence:(2) (3)

    • SUBD WAR

  • utput dependence:(2) (4)

    • MULD WAW

1.DIVD F0,F2,F4

2.ADDD F6,F0,F8

3.SUBD F8,F10,F14

4.MULD F6,F10,F8


  • Scoreboarding

    • 1963 CDC6600 scoreboard

    • WAR hazards

      • Stall WB registers

      • registers Read Operands

    • WAW hazards

      • (issue)

  • Robert Tomasulo's algorithm

    • 1966 IBM360/91

    • WAR WAW hazards register renaming


Register Renaming

DIV.D F0,F2,F4

ADD.D S,F0,F8

S.D S,0(R1)

SUB.D T,F10,F14

MUL.D F6,F10,T

DIV.D F0,F2,F4

ADD.D F6,F0,F8

S.D F6,0(R1)

SUB.D F8,F10,F14

MUL.D F6,F10,F8

DIV.D F0,F2,F4

ADD.D F6,F0,F8

S.D F6,0(R1)

SUB.D T,F10,F14

MUL.D F6,F10,T

DIV.D F0,F2,F4

ADD.D S,F0,F8

S.D S,0(R1)

SUB.D T,F10,F14

MUL.D F6,F10,T


Tomasulo

  • Reservation Stations (RS)

    • operands

    • Functional Units (FUs)

  • source registers RS, input register renaming

    • WAR, WAW hazards

    • RS registers name dependences compiler

  • FU RS, register file, Common Data Bus broadcast FUs

  • Load,Stores FUs RSs


MIPS floating point + load-store unit using Tomasulos algorithm

Reservation Stations:

contain already issued instruction and its operands or the names of the reservation stations that will provide the operand values for this instruction

Load store buffers:

hold the components of the effective address, hold the results of the completed loads, track loads that are waiting on the memory


Tomasulo: MIPS FP-Unit

FP Registers

FP Op

Queue

From Mem

Load Buffers

Load1

Load2

Load3

Load4

Load5

Load6

Store

Buffers

Add1

Add2

Add3

Mult1

Mult2

Reservation

Stations

To Mem

FP adders

FP multipliers

Common Data Bus (CDB)


Tomasulo

Issue: FP Op Queue

RS (no structural hazard), (issue) , operands (rename registers)

Execute: (EX)

operands , . , CDB

Write result: (WB)

CDB . RS


(1)

  • Reservation Station fields

    • Op:

    • Vj, Vk: source operands

    • Qj, Qk: RS source operands

      • , Q V operand

    • Busy: RS


(2)

  • Register Result status

    • Qi : RS register.

  • Load,Store Buffer fields

    • : effective address /

    • Busy: buffer


(3)

  • Common Data Bus

    • data bus: data + destination (go to bus)

    • CDB: data + source (come from bus)

    • 64 bits of data + 4 bits of Functional Unit source address

    • source Q RS, V RS

    • Broadcast: master, slaves


Instruction stream

3 Load/Buffers

3 FP Adder R.S.

2 FP Mult R.S.

FU count

down

Clock cycle counter

Tomasulo Example

(load: 2 cycles, add: 2 cycles, mult: 10 cycles, divide 40 cycles)


Tomasulo Example Cycle 1


Tomasulo Example Cycle 2


Tomasulo Example Cycle 3

  • issue RS, source registers (renamed) V Q RS

  • Load1 - ?


Tomasulo Example Cycle 4

  • Load2 - ?


Tomasulo Example Cycle 5

  • Add1, Mult1 (load: 1 cycle, add: 2 cycles, mult: 10 cycles, divide 40 cycles)


Tomasulo Example Cycle 6

  • ADDD issue name dependency F6


Tomasulo Example Cycle 7

  • o Add1 (SUBD) - ?


Tomasulo Example Cycle 8


Tomasulo Example Cycle 9


Tomasulo Example Cycle 10

  • Add2 (ADDD) - ?


Tomasulo Example Cycle 11

  • ADDD


Tomasulo Example Cycle 12


Tomasulo Example Cycle 13


Tomasulo Example Cycle 14


Tomasulo Example Cycle 15

  • Mult1 (MULTD) - ?


Tomasulo Example Cycle 16

  • ... DIVD (div: 40 cycles)



Tomasulo Example Cycle 55


Tomasulo Example Cycle 56

  • Mult2 (DIVD) - ?


Tomasulo Example Cycle 57

  • : In-order issue, out-of-order execution out-of-order completion.


Tomasulo Loop Example

Loop:LDF00R1

MULTDF4F0F2

SDF40R1

SUBIR1R1#8

BNEZR1Loop

  • mult: 4 cycles

  • 1st load: 8 cycles (L1 cache miss)

  • 2nd load: 4 cycles (hit)

  • branch


Iter-

ation

Count

Store Buffers

Instruction Loop

Loop Example


Loop Example Cycle 1


`

Loop Example Cycle 2


Loop Example Cycle 3


Loop Example Cycle 4

  • ( SUBI - FP queue- dispatch)


Loop Example Cycle 5

  • ( BNEZ)


Loop Example Cycle 6

  • F0 load 80


Loop Example Cycle 7

  • register file

  • 1 2


Loop Example Cycle 8


Loop Example Cycle 9

  • Load1 - ?

  • ( SUBI dispatch)


Loop Example Cycle 10

  • Load2 - ?

  • ( BNEZ dispatch)


Loop Example Cycle 11

  • load


Loop Example Cycle 12

  • issue mult?


Loop Example Cycle 13

  • issue store?


Loop Example Cycle 14

  • Mult1 - ?


Loop Example Cycle 15

  • Mult2 - ?


Loop Example Cycle 16

  • issue 3MULTD


Loop Example Cycle 17

  • issue 3SD


Loop Example Cycle 18

  • 1SD


Loop Example Cycle 19

  • 2SD


Loop Example Cycle 20

  • : In-order issue, out-of-order execution out-of-order completion


?

  • Register renaming

    • destination registers (dynamic loop unrolling).

  • Reservation stations

    • issue integer control loop

    • buffer registers stalls WAR hazards


  • hazards

    • reservation stations

    • 1 ( operand ), broadcast CDB

      • register file, , register bus

  • stalls WAW WAR hazards

    • register renaming reservation stations


Explicit Register Renaming(1)

  • : registers register renaming;

  • :

    • physical register file physical register ISA registers

    • Translation Table ( )

    • physical registers


Fetch

Decode/

Rename

Execute

Rename

Table

Explicit Register Renaming(2)

  • pipeline 5-stage pipeline

  • decode ISA register physical register.

    • target : registers Register Map Table (RMT)

    • source : X RMT

  • physical register , .


Instruction Stream

Register Map Table

Free Registers

DIVR5,R4,R2

ADDR7,R5,R1

SUBR5,R3,R2

LDR7,1000(R5)

PR37,PR4,PR42,PR19,...


(1)

Instruction Stream

Register Map Table

Free Registers

DIVR5,R4,R2

ADDR7,R5,R1

SUBR5,R3,R2

LDR7,1000(R5)

PR37,PR4,PR42,PR19,...

DIVPR37,PR45,PR2


(2)

Instruction Stream

Register Map Table

Free Registers

DIVR5,R4,R2

ADDR7,R5,R1

SUBR5,R3,R2

LDR7,1000(R5)

PR4,PR42,PR19,...

DIVPR37,PR45,PR2

ADDPR4 ,PR37,PR23


(3)

Instruction Stream

Register Map Table

Free Registers

DIVR5,R4,R2

ADDR7,R5,R1

SUBR5,R3,R2

LDR7,1000(R5)

PR42,PR19,...

DIVPR37,PR45,PR2

ADDPR4 ,PR37,PR23

SUBPR42,PR17,PR2


(4)

Instruction Stream

Register Map Table

Free Registers

DIVR5,R4,R2

ADDR7,R5,R1

SUBR5,R3,R2

LDR7,1000(R5)

PR19,...

DIVPR37,PR45,PR2

ADDPR4 ,PR37,PR23

SUBPR42,PR17,PR2

LDPR19,1000(PR42)


  • reservation stations

  • renaming scheduling

    • pipeline 5-stage pipeline

  • register file

  • WAR,WAW hazards

  • E ( Tomasulo) out-of-order completion

  • explicit register renaming + Tomasulo


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