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Current: Sum of the currents at any node must equal 0.
Currents Entering = Currents Exiting
Voltage:Sum of the voltages in a circuit loop must equal 0.
Voltages Supplied = Voltages Dropped
Recall the Basic Kirchhoff’s Circuit Laws
Parallel Resonance (Infinite Impedance)
Parallel Impedance Z = sL // (sC)1
Z = (sL)(sC)1 / (sL + (sC)1)
Z = sL / (s2LC + 1) jwL / (w2LC + 1)
Note Z Infinity when w2 = LC w = (LC)1/2
(f = 2pw )
Series Resonance (Zero Impedance)
Series Impedance Z = sL + (sC)1
Z = s2LC + 1 w2LC + 1
Note Z 0 when w2 = LC w = (LC)1/2
Simple Small Signal Models for the BJT
Figure 4.33 Smallsignal equivalent circuits for the BJT.
Common Emitter Amplifier & Small Signal Equivalent Circuit
Voltage Gain: Av = vO/vIN =  bAC (RC//RL)
(rp + (1 + bAC)RE1)
Current Gain: Ai = iO/iIN =  bAC RC(R1//R2)/(RC+RL)
(rp + (1 + bAC)RE1) + (R1//R2)
Input Impedance: Ri = vIN/iIN = (R1//R2)//(rp + (1 + bAC)RE1)
Transistor Amplifier Load Line Analysis
VCC/RDC
VCC
DC or Static Load Line:VCC = ICRC + VCEq + (IC + IB)RE Note IC = (bDC)IB & RE = RE1 + RE2
VCC = IC (RC + RE + RE/ bDC) + VCEq = IC (RDC) + VCEqwhere RDC = RC + RE + RE/ bDC
Now put into the form Y = mX = b where Y = IC & X = VCE
IC = VCE (RDC )1 + VCC (RDC )1 Y intercept = VCC/RDC X intercept = VCC
Transistor Amplifier Load Line Analysis
The AC or Dynamic Load Line shows the slope the amplifier will actually operate on with signal swing
Transistor Amplifier Load Line Analysis
Yd
Ys
Q
Xd
Xs
Load Line Comparison:
Static: IC = VCE (RDC )1 + VCC (RDC )1 Ys = VCC/RDC Xs = VCC
Dynamic: IC = VCE (RAC )1 + (VCEq/RAC + ICq ) Yd = VCEq/RAC + ICq Xd = VCC  ICq (RDC RAC)
Quiescent Point Q will be at Intersection, For Best Q Point  Bisect the AC Load Line End Points
Note: For Capacitively Coupled Loads RAC < RDC
Therefore Set ICq = VCC/(RDC + RAC)
Additional Parameters

Operational Amplifier – Why?Linear, Differential, High Gain AmplifierAdvantages Over Single Ended Amplifier Block ??

Operational AmplifierIdeal AssumptionsVp
Used for basic analysis, nominal gain analysis
Vout
These basic assumptions allow simple circuit analysis to determine Nominal gain applications
Vn

Operational AmplifierPower SuppliesVcc
Vp
Power Supplies can be a critical consideration
Vout
Vn
Vcc

Operational AmplifierBasic ApplicationsRf
Av =  Rf/Ri
Zin = Ri
Inverting Voltage Amp
Ri
Vin
Vout
Rp

Operational AmplifierBasic ApplicationsRi
Av = 1 + Rf/Rp
Zin = Ri +
NonInverting Voltage Amp
When Rf=0, Rp=~Infinite…… Av = 1
Vin
Vout
Rf
Rp
8

Operational AmplifierBasic ApplicationsRi
Gm = 1/Rp
Zin = Ri +
Transconductance Amp
Vin
RL
Iout
Rp
8

Operational AmplifierIdeal AssumptionsVp
Used for basic analysis, nominal gain analysis
Vout
These basic assumptions allow simple circuit analysis to determine Nominal gain applications
Vn

Operational AmplifierReal CharacteristicsIp
Vp
Vout
Used for more accurate
Gain Characterization
Iout
Vio
Ad is the diff gain, Ac is the common mode gain, Vio = offset voltage
Use superposition to understand contributions
In
Vn

Operational AmplifierReal Characteristic EffectsBasic Strategy
Vp
Vout
Vn

Inverting ConfigurationOffset Error Contribution 1Rf
Ii = (0Vio)/Ri
If = (VioVo)/Rf
Ii = If
Vo = Vio(1 + Rf/Ri) = Verr
Inverting Voltage Amp
Error Voltage due to Vio
Ri
If
Vout
Vio
Ii
Rp

Noninverting ConfigurationOffset Error Contribution 1Ri
Ii = (0Vio)/Rp
If = (VioVo)/Rf
Ii = If
Vo = Vio(1 + Rf/Rp) = Verr
NonInverting Voltage Amp
Error Voltage due to Vio
Vin
Vout
Vio
Rf
If
Rp
Ii
IO
~10 deg C

Inverting AmplifierOffset Error Contribution 2Rf
At V+: Iio = Ib + V+/Rp
V+ = Rp(IioIb)
At V: V/Ri = (VVout)/Rf + Ib + Iio
Sub V+ into above equation
Vo = Verr = Rf(Ib/+Iio)  [((RfRp)/Ri + Rp)(Ib+/Iio)]
Note if Iio = ~0 and Rp = Rf//Ri, then Verr = 0
Verr is always minimized when Rp = ~Rf//Ri
Inverting Voltage Amp
Error Voltage due to Ib, Iio
Ri
If
Vin
Vout
Iio
Ii
Ib
Ib
Rp

NonInverting AmplifierOffset Error Contribution 2Rf
At V+: Iio = Ib + V+/Ri
V+ = Ri(IioIb)
At V: V/Rp = (VVout)Rf + Ib + Iio
Sub V+ into above equation
Vo = Verr = Rf(Ib/+Iio)  [((RfRi)/Rp + Ri)(Ib+/Iio)]
Note if Iio = ~0 and Ri = Rf//Rp, then Verr = 0
Verr is always minimized when Ri = Rf//Rp
NonInverting Voltage Amp
Error Voltage due to Ib, Iio
Rp
If
Vout
Iio
Ip
Ib
Ib
Ri
Ii
Vin

Inverting AmplifierGain ErrorRf
Av (nom) =  Rf/Ri
But Assume Vout = Ad(V+  V)
Find expressions for V+ & V
Substitute into above Vout
Solve for Vout/Vin = Av
Av = (RfAd)/(RiAd + Ri + Rf)
Av = Av(nom)/CF
CF = Correction Factor
CF = 1 + 1/Ad + Rf/(RiAd)
Av < Av (nom)
Inverting Voltage Amp
Ri
If
Vin
Vout
Ii
Rp
Don’t Forget to Factor in Res Tol% !

NonInverting AmplifierGain ErrorRi
Vin
Vout
Av (nom) = 1+ Rf/Rp
But Assume Vout = Ad(V+  V)
Find expressions for V+ & V
Substitute into above Vout
Solve for Vout/Vin = Av
Av = Ad(Rp + Rf)/(RpAd + Rp + Rf)
Av = Av(nom)/CF
CF = Correction Factor
CF = 1 + 1/Ad + Rf/(RpAd)
Av < Av (nom)
NonInverting Voltage Amp
Rf
Rp
Don’t Forget to Factor in RTol% !

Operational AmplifierGain ErrorRf
Ri
If
Vin
Vout
Ii
Largest Error will be due to Rtol !!Gain Error = Av(nom) – Av
Verr from Gain Error
Verr = Vin(max) * Gain Error
Rp
0.1V
Vout
10K 1%
+

1K
1%
ExampleNominal Gain = 1+Rf/Ri = +11.0
Nominal Output = 1.1V
TLO72C
0.1V
Vout
10K 1%
+

1K
1%
Analysis requires opamp data sheet infoTLO72C
0.1V
Vout
10K 1%
+

1K
1%
NonInverting AmplifierGain ErrorAv (nom) = 1+ Rf/Rp = 11.0
Av (min) Rf down 1% 9.9KW,
Rp up 1% 1.01KW
Av = Ad(Rp + Rf)/(RpAd + Rp + Rf)
Av = Av(nom)/CF
CF = Correction Factor
CF = 1 + 1/Ad + Rf/(RpAd)
TLO72C
Av(min) = 15K(1.01+9.9) / [(15K)(1.01) + 9.9 + 1.01] = 10.79 Error from nominal = (0.1V)(11.0 – 10.79) = 0.021 21mV
Av(max) = 1 + (10.1 / 0.99) = 11.20 (Assume Ad is max) Error from nominal = (0.1V)(11.20 – 11.0) = 0.020 20mV
Worst Case Gain Error assuming Vin = 0.1V = 20mV or 21mV
0.1V
Vout
10K 1%
+

1K
1%
Noninverting ConfigurationOffset Error Contribution 1Verr1 = Vio(1 + Rf/Rp)
Verr1a(max) = 13mV(1 + 10.1/0.99) = 145.6mV
Verr1b(max) = 13mV(1 + 9.9/1.01) = 140.4mV
TLO72C
Worst Case Offset 1 Error = 145.6mV or 140.4mV
0.1V
Vout
10K 1%
+

1K
1%
NonInverting AmplifierOffset Error Contribution 2Verr2 = Rf(Ib/+Iio)  [((RfRi)/Rp + Ri)(Ib+/Iio)]
Verr2 = 10(7nA/+2nA) – [(10)(10)/1 + 10](7nA+/2nA)
Verr2 worst case = ~1mV
TLO72C
Worst Case Offset 2 Error = ~1mV
Answer: Worst Case Total Error = 165.6mV (when Rf = max, Rp = min)

Operational AmplifierGain vs Bandwidth TradeoffRf
Av =  Rf/Ri = Nominal Closed Loop Gain
Ad (Opamp) = Open Loop Gain
Ri
Vin
Vout
Rp
Potential Filter Shapes
Potential Filter Shapes
Potential Filter Shapes
Potential Filter Shapes
General 2nd Order Transfer Function where;
4R
+15V
0.1uF
Vo(s)
TLO72C
Vi(s)
0.1uf
15V
C
C
Example4R
+15V
0.1uF
Vo(s)
TLO72C
Vi(s)
0.1uf
15V
C
C
ExampleB
Analysis
A
(VaVo)/4R = VosC Va = Vo(1 + 4sRC)
(ViVa)/R = (VaVo)sC + (VaVo)/4R
Vo
Looks like a Lowpass Filter Transfer Function
At F = 0hz Av = 1
At F = hz Av = 0
8
Substitute and solve for Vo/Vi = Av(s)
Av(s) = 1 / {(2RC)s2 + (5RC)s + 1}
4R
+15V
0.1uF
Vo(s)
TLO72C
Vi(s)
0.1uf
15V
C
C
ExampleB
A
Av(s) = 1 / {(2RC)2s2 + (5RC)s + 1}
Av(jw) = 1 / {(2RC)2w2 + (5RC)jw + 1}
 Av(jw) = 1 / sqrt {Real2 + Imag2}
 Av(jw) = 1 / sqrt { [1(2RCw)2]2 + [5RCw]2 }
/_ Av(jw) = Tan1(Num)  Tan1(Den)
/_ Av(jw) = 0  Tan1(Imag/Real)
/_ Av(jw) = 0  Tan1{[5RCw]/ [1(2RCw)2]}
Vo
Example: R = 10K, C = 0.01uF
F = 100Hz Av = 1.0 AvdB = 0.28
F = 1Khz Av = 0.31 AvdB = 10.09
F = 10Khz Av = 0.006 AvdB = 44.08
F = 100Khz AvdB = 88
1 Decade = 40dB
2nd Order Lowpass Filter
4R
+15V
0.1uF
Vo(s)
TLO72C
Vi(s)
0.1uf
15V
C
C
ExampleB
A
Av(s) = 1 / {(2RC)2s2 + (5RC)s + 1}
Av(s) = 1/(2RC)2 / {s2 +(5/(2RC))s + (1/(2RC)2)}
In the 2nd order form of …
Av(s) = G wo2 /{s2 + (wo/Q)s + wo2}
wo2 = 1/(2RC)2 = wo = 1/2RC Fo = 1/(4pRC)
wo/Q = 5/(4RC) (1/2RC)/Q = 5/(4RC)
Q = 2/5 = 0.40
G wo2 = 1/(2RC)2 G = 1
Vo
Example: Design a 2nd order lowpass filter with Fo = ~800hz
Fo = 1/(4p(10k)(0.01uf)) 795 hz
Let R = 10K, 4R = 40K, C = 0.01uf
Summary of Basic Biquadratic Filter Transfer Functions T(s):
Note: Many texts will define Fo as the –3dB frequency or corner frequency.
However, it is really just the “peak” of the transition band range of the filter as shown on the response curves. The actual value of Av (or T) depends on the damping factor Q of the filter.

+

Classic MultiFunction Filter DesignSumming Inv Amp
Vout BP
Vin
1
R1
C1
R2
C2
1
+
A1
1
Vout HP
A2
Vout LP
Rp
Rp
Inv Amp
B
Typically 2 types of amplifiers are utilized
NonInverting: Phase contribution = 0o = 360o
Inverting: Phase contribution = 180o
R/(1 + sCR) + R + 1/sC
sCR
(sCR)2 + 3sCR + 1
(1 + R2/R1)(sCR)
(sCR)2 + 3sCR + 1
Wein Bridge OscillatorRC Feedback Network Gain
R//(1/sC)
R//(1/sC) + R + 1/sC
R // (1/sC) R / (1 + sCR)
Total Loop Gain Ab(s)
Total Loop Gain – Magnitude Ab(jw)
(1 + R2/R1)(wCR)
SQRT {[1  (wCR)2]2 + [3wCR]2}
3wCR
1  (wCR)2
3wCR
1  (wCR)2
90o – TAN1
270o – TAN1
(1 + R2/R1)(sCR)
(sCR)2 + 3sCR + 1
(1 + R2/R1)(jwCR)
 (wCR)2 + 3jwCR + 1
Wein Bridge OscillatorTotal Loop Gain – Steady State Analysis
Total Loop – Phase /_Ab(jw)
Total Loop Phase /_Ab(jw) including inverting amplifier must be 0 to satisfy criterion #2
= 0o
3wCR
1  (wCR)2
 TAN1
Wein Bridge OscillatorTotal Loop Phase /_Ab(jw) including inverting amplifier must be 0 to satisfy criterion #2
= 90o
Can only occur, when;
1  (wCR)2
= 0
w= 1/RC
Total Loop – Magnitude Ab(jw) @ w = 1/RC Must be = 1.0 to satisfy criterion #1
(1 + R2/R1)
SQRT {[3]2}
= 1.0
(R2/R1) = 2.0
If R2/R1 = 2, oscillations occur
If R2/R1 < 2, oscillations attenuate
If R2/R1 > 2, oscillation amplify and then saturate
Diodes D1 and D2 begin conducting when sufficient amplitude is reached at Vo
They effectively combine R4 in parallel with R3 for some of the voltage swing
Improved Automatic Gain Control
Note A is Inverting
Bubba Oscillator (Modified Phase Shift)
Note A is Inverting
+
Comparator CircuitVcc Vcc
Rb
Vin
Vout
Nonlinear opamp output
Vout = Vh or Vout = VL
Vh < Vcc, VL > Vcc
Vh and VL values typically 0.5 to 3V below Vcc
V+ = {(Vout – Vref) (Ri) / (Ri + Rf)} + Vref, V = Vin
Assume Vo = Vh and V+ >V but Vi is increasing
If Vi > (Vout – Vref) (Ri) / (Ri + Rf) + Vref, Vo VL
The upper trip point (Vutp) is found as;
Vutp = {(Vh – Vref) (Ri) / (Ri + Rf)} + Vref
Rf
Ri
Positive Feedback
Hysteresis Resistor
Vref
When V+ > V, then Vo = Vh
When V+ < V, then Vo = VL
Vin is compared against Vref
+
Comparator CircuitVcc Vcc
Rb
Vin
Vout
Nonlinear opamp output
Vout = Vh or Vout = VL
Assume now Vo = VL and V+ <V but Vi is decreasing
If Vi < (VL – Vref) (Ri) / (Ri + Rf) + Vref, Vo Vh
The lower trip point (Vltp) is found as;
Vltp = {(VL – Vref)(Ri) / (Ri + Rf)} + Vref
Rf
Ri
Positive Feedback
Hysteresis Resistor
Vref
When V+ > V, then Vo = Vh
When V+ < V, then Vo = VL
Vin is compared against Vref
+
Comparator Circuit Example+Vcc Vcc
Rb
Vin
Vout
Vltp = {(VL – Vref)(Ri) / (Ri + Rf)} + Vref
Vutp = {(Vh – Vref)(Ri) / (Ri + Rf)} + Vref
Rf
Vh
Ri
Vref
Vref
Vltp
Vutp
The rectangular shape is known as a
Hysteresis Diagram
Vl
+
Comparator Circuit Example+15V 15V
10K
Vin
Vout
Vltp = {(13 – 5) (10k) / (10k + 100k)} + 5
Vltp = 3.36V
Vutp = {(13 – 5) (10k) / (10k + 100k)} + 5
Vutp = 5.73V
100K
Vh = ~13V
VL = ~13V
13v
10K
5v
Vref = 5V
3.36v
5.73v
Vhyst = Vutp – Vltp = 2.37V
13v
+
Controlling Vh and VL voltagesVcc Vcc
Rb
RL
Vin
Vh or VL
Must have current limiting
Resistor RL when using a
Voltage Clamp
(VhVout)/RL < Imax for opamp
Imax (typical) = ~ 5mA
Vout
Rf
Voltage
Clamp
Ri
Positive Feedback
Hysteresis Resistor
Vref
Controlling Vh and VL give greater utility for Comparator
RL
Diode String Clamp
Vh = Vd1+Vd2+Vd3 = ~2.1v
VL = Vd4Vd5 = ~1.4v
D1
D4
D1
Vout
D4
Z1
Z1
D2
Voltage
Clamp
D5
D2
Z2
D3
D3
Stacked Zener Clamp
Vh = Vd1+Vz2
VL = Vz1Vd2
Zener Bridge Clamp
Vh = Vd1+Vd2+Vz1
VL = Vd3Vd4Vz1
Vh = VL
Types of Voltage Clamps
+
Controlling Vh and VL voltagesVcc Vcc
Rb
RL
Vin
Vh or VL
Vout
Rf
Vh
Voltage
Clamp
Ri
Positive Feedback
Hysteresis Resistor
Vref
Vref
Vutp
Vltp
NOTE: If Vh < Vref, Vref may be outside of VltpVutp window
But hysteresis will still work
Vl
+
Schmitt Trigger  ComparatorVcc Vcc
Rb
Vin
Vout
Vltp = (VL) (Ri) / (Ri + Rf)
Vutp = (Vh) (Ri) / (Ri + Rf)
Rf
Ri
Vref = 0
In a Schmitt Trigger, Vref = 0V
+
C
Comparator – RC OscillatorR2
D2
D1
R1
Vcc Vcc
Rb
Vin
RL
Vout
Rf
Voltage
Clamp
Ri
Vref = 0
Schmitt Trigger used in a Relaxation Oscillator
D2
D1
R1
Vcc Vcc
Rb
Vin
RL
Vout

+
C
Rf
Voltage
Clamp
Ri
Vref = 0
Comparator – RC OscillatorTh = (R1C) ln{(VutpVhVd1)/(VltpVh+Vd1)}
TL = (R2C) ln{(VltpVLVd2)/(VutpVL+Vd2)}
Note:
For Ri = Rf = Rb, R1//R2 = R, No Diodes & Vh = VL
Vutp = Vltp = 1/2Vh
Th = (RC) ln {(VutpVh)/(VltpVh)} = RC ln (1/3)
TL =  RC ln (1/3)
F = 1 / {2RC ln (1/3)} = 0.455/RC
Individual High and Low Times can be set with Th & TL
D2
D1
R1
Vcc Vcc
Rb
Vin
RL
Vout

+
C
Rf
Voltage
Clamp
Ri
Vref = 0
Comparator – RC OscillatorVh
Th
Vutp
0
Vltp
TL
VL
Capactor Voltage & Output Waveforms
Typical Linear Regulator Circuit
Pass Transistors May be Reconfigured for LDO or Low Dropout Performance
Note: Power Dissipated = (VinVout)Iin
Typical Thermal Shutdown Protection System
Pass Transistor is Forced Off in Thermal Shutdown
Most low cost regulators do NOT latch this condition
BuckBoost Inverting Switching Regulation System Architecture
Coasting Diode Conducts Inductor Current during the Switch Off Cycle which pulls current from Load creating a negative polarity on the Capacitor
Coasting Diode is reverse biased during the Switch On Cycle. Capacitor C continues load current direction due to negative charge
Capacitor Equiv Circuit Architecture
With Parasitics Modeled
Basics of Converter Technology
ANALOG VOLTAGE RANGE
VFS
QUANTIZED INTO
2n LEVELS
WHERE n = # OF BITS
Nominal Quantization Step
0 1 2 3 4 5 6 7 8 9 10 11
Nominal Step Size Q = VFS/2n
Highest Voltage Step = VFS – Q
Max Count = 2n–1 (0 is a valid step)
Quantization Error Architecture
Note: Last step occurs at VFS(N1)/N under ideal conditions
Voltage is Measured as Fraction of a reference Vref
VFS = Vref
Quantization Error
Ideal 3 Bit A/D Converter Transfer Function
SNR = 20 log(2 Architecture(n1) * sqrt(6) )
= 20log (2(n1)) + 20log (sqrt(6))
= 20(n1)log(2) + 20log (sqrt(6))
= 20nlog(2)20log(2)+20log (sqrt(6))
= 20nlog(2) + 20log (sqrt(6)/2)
= 6.02n + 1.76
n
D/A
A/D
Sinewave MAX SNRDB = 6.02n + 1.76
Converter Offset Error Architecture
Converter Gain Error Architecture
Integral Linearity Error: Max Deviation from Ideal Straight Line
(INL: Integral NonLinearity)
Xfer Curve drawn at midpoint of each input step (ideal vs actual)
Differential Linearity Error: Max Deviation from Ideal Step Size
(DNL: Differential NonLinearity)
DNL max > 1 Bit can lead to missing codes
In Ideal Converter ENOB = n
Power Supplies are Extremely Important !! Size
A/D Converter Architectures Size
Successive Approximating (SAR) Size
END OF CONV
SUCCESSIVE
APPROXIMATION
REGISTER
n1
n2
n3
Decision signal
n
OUTPUT
BITS
CONTROL
CLOCK
Clock
nn
V Ref
n1
B
BIT
D/A
Converter
COMPARATOR
n2
n3
Buffer
V in
nn
Integrating Size
COUNTER
n1
n2
n Output Bits
n3
Buffer
V in
nn
CLOCK
Clk
COMPARATOR
Clr
Current
Source
CONTROL
I
C
FLASH Size
V Ref
OUTPUT
LOGIC
REGISTER
n1
n2
n1
n Output Bits
n2
BUFFER
V in
n3
nn
2n –1 COMPARATORS
1
In early bipolar versions, R = 5K, hence the “555” name
Pulse Generator Application of Typical 555 Timer IC
Relaxation Oscillator Application of Typical 555 Timer IC