UNH InterOperability Lab

1. UNH InterOperability Lab Serial ATA (SATA)Clause 9 Considerations

2. Presentation Topics • 8b10b Encoding • SATA Primitives • ALIGN use in SATA • HOLD use • CONT use • Frame Delivery Handshake • Scrambling

3. 8b10b Encoding • All information transmitted over SATA is encoded into a 10-bit character and sent serially bit by bit. • 1024 possible 10-bit characters. • 256 of these possible 1024 characters are data characters. • Some of these 1024 characters are control characters. • The remaining 10-bit characters are invalid.

4. 8b10b Encoding Conventions • An unencoded information byte is composed of: • a) eight information bits labeled A, B, C, D, E, F, G, and H. Each information bit contains either a binary zero or a binary one • b) a control variable labeled Z. A control variable has either the value D or the value K • D means the information byte is a data byte • K means the information byte is a control byte

5. 8b10b Encoding Conventions • In other words:

6. 8b10b Encoding Conventions • Encoded in Zxx.y • Z=D or K • xx=decimal number value of binary number composed of E,D,C,B,A • y= decimal number value of the binary number composed of H,G,F

7. Bit Transmission Order • An information byte is encoded into a 10-bit character containing bits labeled a, b, c, d, e, i, f, g, h, and j. Bit a shall be transmitted first, followed by bits b, c, d, e, i, f, g, h, and j, in that order.

8. Dwords • Dwords are 4 bytes of data. • The first, or least significant byte, is byte 0. • Comma characters always occur in the first byte of a dword. • In SATA the only comma character is the control character K28.5. • Dwords are aligned on 4 byte boundaries using comma characters as a byte 0 reference.

9. SATA Primitives • Primitives are a type of Dword entity used to control and provide status of the serial line. • Primitives always begin with a control character. • The SATA ALIGN primitive is the only primitive to contain the comma character K28.5.

10. Character Transmission Order • Characters within primitives shall be transmitted sequentially beginning with the control character used to distinguish the primitive and proceeding character by character from left to right Example (ALIGN Primitive): K28.5 D10.2 D10.2 D27.3

11. ALIGN Primitives • ALIGN: K28.5 D10.2 D10.2 D27.3 • The link layer shall ignore reception of ALIGN primitives. • The phy layer shall remove ALIGN primitives from the bit stream before forwarding them to the link layer. • ALIGN primitives are important at the phy layer.

12. HOLD Primitives • HOLD: K28.3 D10.5 D21.4 D21.4 • HOLD is transmitted in place of the transmitted payload data in a frame when the transmitter does not have the payload data ready for transmission. • HOLD is also transmitted by the receiver when the receiver is not ready to receive additional payload data.

13. HOLD Primitives • HOLDA: K28.3 D10.5 D21.4 D21.4 • HOLDA is transmitted in response to HOLD as an acknowledgment.

14. CONT Primitives • CONT: K28.3 D10.5 D25.4 D25.4 • In order to reduce EMI, scrambling of data is incorporated in Serial ATA. • It is not practical to scramble primitives • Any repetitive primitive may be implied to continue repeating through the use of CONT.

15. CONT Primitives • After the transmission of CONT, the transmitter may send a sequence of data characters to the recipient if the sequence contains no primitives. • The recipient of CONT shall ignore all data received until any primitive is received, excluding ALIGN primitives. • The recipient assumes every DWORD after the reception of CONT, to be the last valid primitive received before the reception of CONT.

16. Scrambling • Scrambling is performed on Dword quantities. • Dwords are scrambled by XORing the data with the output of a Linear Feedback Shift Register (LFSR).

17. Scrambling – LFSR

18. Scrambling • The LFSR is to be initialized to the seed value of FFFFh before the first shift of the LFSR. • The LFSR shall be initialized to the seed value before an SOF primitive is transmitted.

19. SATA Frame • A frame starts with an SOF primtive, followed by a user payload called a Frame Information Structure (FIS), a CRC and ends with an EOF primitive. • The CRC is defined as the last non-primitive DWORD before the EOF primitive. Its value is calculated from the data contained in the preceding FIS.

20. SATA Frame • HOLD and CONT primitives are the only primitives allowed between an SOF and EOF primitive (CONT is used to repeat HOLD primitives). They are use for flow control and speed matching purposes.

21. Frame Delivery Handshake • The diagram on the following slide is a simplified state diagram of the SATA frame delivery handshake from the transmitter’s perspective. • The simplified state diagram assumes there were no errors and that the handshake completed successfully from start to finish. All error states are excluded in the simplified diagram.

22. Simplified Handshake (TX Perspective)

23. State Breakdown HL_SendChkRdy • This is the first state in the receipt of a frame by a host. Transmits X_RDY until an R_RDY, X_RDY or PHYRDYn is received. Typical next state is L_SendSOF. DL_SendChkRdy • This is the first state in the receipt of a frame by a device. Transmits X_RDY until R_RDY or PHYRDYn is received. Typical next state is L_SendSOF.

24. State Breakdown L_SendSOF • Transmits a single SOF primitive before progressing to the next state. Typical next state is L_SendData.

25. State Breakdown L_SendData • Transmits data while HOLD, DMAT or SYNC are being received. • Transitions to L_RcvrHold if HOLD is received. • Transitions to L_SendHold if there is more data to be sent but it isn’t ready. • Transitions to L_SendCRC if DMAT is received or data transmission is complete and any Dword other than SYNC is received. • Transitions to L_IDLE if SYNC is received.

26. State Breakdown L_SendCRC • Transmits the one Dword CRC. • Progresses to L_SendEOF if PHYRDY and if SYNC not received. • Goes to L_IDLE state if PHYRDY and if SYNC is received. • Goes to L_NoCommErr state on PHYRDYn.

27. State Breakdown L_SendEOF • Transmits an EOF primitive. • Progresses to L_IDLE state if PHYRDY and SYNC received. • Goes to L_Wait state if PHYRDY and SYNC not received. • Goes to L_NoCommErr state on PHYRDYn.

28. Zoom in on sections of above diagram and add detailed description. • In later slides explain the overall state machine and the error states. • PHYRDY The Phy logic and main PLL are both on and active. The interface is synchronized and capable of receiving and sending data. • PHYRDYn: The negation of the PHYRDY signal.