Programmable/Stoppable Oscillator Based on Self-Timed Rings

1. Programmable/Stoppable Oscillator Based on Self-Timed Rings ASYNC 2009, UNC Chapel hill • Eslam Yahya1,4, Oussama Elissati1,3, Hatem Zakaria1,4 , • Laurent Fesquet1 and Marc Renaudin2 • 1TIMA Laboratory, Grenoble, France • 2TIEMPO, Montbonnot, France • 3ST-Ericsson, Grenoble, France • 4Banha High Institute of Technology, Banha, Egypt

2. Context and Motivation • Process variability increases drastically in the 45 nm technologies and beyond. • Application of DVFS techniques is essential.  Programmable oscillators are needed • Self –Timed Rings are promising solutions for: • Reconfigurability. • Process Variation. • However, no programmable oscillators based on Self-Timed Rings are introduced in the literature. ASYNC 2009, UNC Chapel Hill

3. Outline • Self-timed rings • Oscillation Frequency Modeling and Calculation • Architecture of Programmable Self-Timed Ring • Programmable-Stoppable Oscillator • Implementation and results • Conclusion and Future Work ASYNC 2009, UNC Chapel Hill

4. Dff 1 1 1 T B T C C C C Drr Self-Timed Ring 0 T B • Tokens and bubbles • Propagation rules ASYNC 2009, UNC Chapel Hill

5. Oscillation modes Two Oscillation Modes • Burst mode • Evenly Spaced Mode ASYNC 2009, UNC Chapel Hill

6. Timed VHDL Model • Programmable Ring  So many simulations. • Contradiction between digital simulation and analog simulation. • Simulating the same ring with the same number of tokens and bubbles, with tow different spatial token distributions. •  Analog : same steady state waveform. •  Digital : different steady state waveform. TBBBBTTBBBT TTTTBBBBBBB 11 stage 4 Tokens/7 Bubbles ASYNC 2009, UNC Chapel Hill

7. Charlie effect • An explanation of this difference between digital and analog simulation is needed. •  Charlie effect!!?? • The closer the input events; the longer the propagation time, causing the separation of the tokens in the ring. 2D Charlie Diagram ASYNC 2009, UNC Chapel Hill

8. Timed VHDL Model Without Charlie Effect TBBBBTTBBBT TTTTBBBBBBB 11 stage 4 Tokens/7 Bubbles With Charlie Effect TBBBBTTBBBT TTTTBBBBBBB 11 stage 4 Tokens/7 Bubbles ASYNC 2009, UNC Chapel Hill

9. Outline • Self-timed rings • Oscillation Frequency Modeling and Calculation • Architecture of programmable Self-Timed Ring • Programmable-Stoppable Oscillator • Implementation and results • Conclusion and Future Work ASYNC 2009, UNC Chapel Hill

10. Modeling and Calculation T = 2N . DInv • Estimating the oscillation period in Inverter Ring: • Estimating the oscillation period in Self-Timed Rings: Where: s is the separation time between input events • Deriving an equation: T = 4 . Charlie(R) = f (Drr , Dff , R) • Charlie(R) is derived. T = 4 . Charlie(s) T = f (Drr, Dff, s) R = NT/NB s = f (R) s = f (NT/NB) ASYNC 2009, UNC Chapel Hill

11. If   If Charlie(R) Charlie from Charlie(s) Charlie from Charlie(R) Error < 1% ASYNC 2009, UNC Chapel Hill

12. Comparison with analog simulation ASYNC 2009, UNC Chapel Hill

13. Outline • Self-timed rings • Oscillation Frequency Modeling and Calculation • Architecture of programmable Self-Timed Ring • Programmable-Stoppable Oscillator • Implementation and results • Conclusion and Future Work ASYNC 2009, UNC Chapel Hill

14. PSTR : Programmable Self-Timed RingStrategy 1 (Token/bubble configuration) • Fixed No. of stages. • Frequency is controlled by changing (NT/NB). Token Control Word Reset Set Reset Reset Set Set From Stage (n-1) Req Req Cn C1 C2 Ack From Stage (3) To Stage (n-1) Ack Stage n Stage 1 Stage 2 ASYNC 2009, UNC Chapel Hill

15. PSTR : Strategy 2 • Variable No. of stages with controllable NT/NB. Token Control Word Reset Set Reset Reset Set Set From Stage (n-1) b Req b Req M1 M2 a Cn a C1 C2 Ack From Stage (3) To Stage (n-1) Ack Stage n Stage 1 Stage 2 To AND of Stage (3) D1 T1 T2 SCW2 SCW1 SCW0 Stage Control Word ASYNC 2009, UNC Chapel Hill

16. Outline • Self-timed rings • Oscillation Frequency Modeling and Calculation • Architecture of programmable Self-Timed Ring (PSTR) • Programmable-Stoppable Oscillator • Implementation and results • Conclusion and Future Work ASYNC 2009, UNC Chapel Hill

17. Programmable/ Stoppable Oscillator (PSO) • A complete architecture of PSO is designed and implemented. Asynchronous communication protocol between the processor and the PSO. • The processor can Pause/Reprogram the PSO output. • The protocol is taking into consideration Metastability and racings. ASYNC 2009, UNC Chapel Hill

18. Interface between µ-Processor and PSO FC … Frequency Code CF … Change Frequency CFD … Change Frequency Done Signal PC …Pause Clock PCD … Pause Clock Done Signal Reset Top Control + Micro-Processor FC CF PC Programmable/Stoppable Oscillator “PSO” FC CF PC CLK CFD Reset PCD Interface between µ-Processor and PSO ASYNC 2009, UNC Chapel Hill

19. Programmable/ Stoppable Oscillator (PSO) FC CF PC Reset Control Unit FC CF PC Reset PCD CFD TCW SCW R_out Stop Reset Programmable Self-Timed Ring “PSTR” + C R_out CLK CFD PCD ASYNC 2009, UNC Chapel Hill

20. Control Unit TCW … Token Control Word SCW … Stage Control Word R_Out … PSTR Ring Output FC CF PC Reset CF Reset LUT 1 LUT 2 Reset (Asy.) Reset (Asy.) Count_Ref D-FF Reset EQ Comparator CF EQ D Q Stop Stop Counter Stop Reset Delay 1 Delay 2 CFD PCD Stop R_Out TCW SCW Control Unit ASYNC 2009, UNC Chapel Hill

21. Outline • Self-timed rings • Oscillation Frequency Modeling and Calculation • Architecture of programmable Self-Timed Ring(PSTR) • Programmable-Stoppable Oscillator • Implementation and results • Conclusion and Future Work ASYNC 2009, UNC Chapel Hill

22. H F A D G B C Timing Diagram of the PSO ASYNC 2009, UNC Chapel Hill

23. Analog Results of the PSO Implemented Using 45 nm STMicroelectronics Technology Low Frequency … 10Tokens/1Bubble High Frequency … 6Tokens/5 Bubbles ASYNC 2009, UNC Chapel Hill

24. Results for Different Strategies Strategy 3: is a partial control on the number of stages ASYNC 2009, UNC Chapel Hill

25. Frequency vs. Supply Voltage • Ring could not oscillate under 0.5V. • A linear change of frequency from 0.8V to 1.1V. ASYNC 2009, UNC Chapel Hill

26. 250 mu = 2.69757 sd = 205.025M N = 1000 200 150 Density 100 50.0 Frequency 0.0 2.0 2.25 2.5 2.75 3.0 3.25 3.5 3.75 1.75 Process Variability of the PSTR • Montecarlo Simulation 1000 Iterations • Average value of 2.6 GHz • Process variability effect on the clock period: • 1% Within Die • 7,6% Die to Die ASYNC 2009, UNC Chapel Hill

27. Outline • Self-timed rings • Oscillation Frequency Modeling and Calculation • Architecture of programmable Self-Timed Ring(PSTR) • Programmable-Stoppable Oscillator • Implementation and results • Conclusion and Future Work ASYNC 2009, UNC Chapel Hill

28. Conclusions • Self Timed Ring is used as a core of programmable oscillator. • For facilitating accurate and fast design environment, timed VHDL models and Charlie(R) are introduced. • Programmability is introduced to Self-Timed Rings using different strategies. • PSO is designed and implemented using STMicroelectronics 45nm CMOS technology. • Asynchronous handshaking protocol between the processor and the oscillator is proposed. • PSO shows glitch free and no truncated clocks at its output. • The implemented chip is characterized for its speed, power consumption and sensitivity to process variability. ASYNC 2009, UNC Chapel Hill

29. Future Work • Adding a voltage controller to the power supply. • Some special implementations for high-speed C-Elements. • More investigation on the phase noise. • Comparing the use of PSTR and some other alternatives. ASYNC 2009, UNC Chapel Hill

30. Thank You ASYNC 2009, UNC Chapel Hill