Sequential redundancy removal w o state space exploration
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Sequential Redundancy Removal w/o State Space Exploration. A. Mehrotra, S. Qadeer, V. Singhal, R. Brayton, A. Aziz, A. Sangiovanni-Vincentelli, “ Sequential Optimization Without State Space Exploration ” ICCAD 97, November 1997 . M. Iyer, D. Long and M. Abramovici,

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Sequential Redundancy Removal w/o State Space Exploration

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Sequential redundancy removal w o state space exploration

Sequential Redundancy Removal w/o State Space Exploration

A. Mehrotra, S. Qadeer, V. Singhal, R. Brayton, A. Aziz, A. Sangiovanni-Vincentelli,

“Sequential Optimization Without State Space Exploration”

ICCAD 97, November 1997

M. Iyer, D. Long and M. Abramovici,

“Identifying Sequential Redundancies without Search”, DAC June 1996


Outline

Outline

  • Compatible Redundancies

    • Combinational

    • Sequential

  • Results


Incompatible redundancies

n1

out

n

n2

(* means unobservable)

n1=0

n2=*

n2 is s-a-1 redundant

n1=1

n2=1

incompatible redundancies

similarly for n1 (s-a-1 redundant)

but setting them both to 1 at the same time gives wrong circuit

Generally, we know that we can find a number of redundancies at once, but setting any one of them to their constant may invalidate the other redundancies.

Like don’t cares. They need to be compatible if they are to be used simultaneoously.


Recursive learning

b1

d

b

f

a1

c

g

a

a2

e

b2

d=0  f = 0

a=1  a1=1

d=1  f = *

f is s-a-0 redundant

Recursive learning

a=0  f=0

recursive

learning


Initial state

Initial state?

  • We will not use an initial state

  • Instead we use concept of c-cycle redundancy

    • after c cycles of clocking, old and new machines have same I/O behavior

    • use concept of safe-delayed replacement which preserves concept of initializing sequences.

Definition: An assumptionA on a set of signals P is a labeling from {0,1} on P


Implications

Implications

AND / INV

1

0

b  b’

1

0

1

b’  b

0 (1)

1

1

0

1

0

1

0 (1)

Observability

Note: a *

can only

imply a *

*

*

0

*

*

*

*


Incompatible redundancies1

c

1

e

1

0

a

b

1

*

0

1

d

*

0

*

*

Incompatible redundancies

0

1

0

  • Obviously wrong because of overwriting

  • When is overwriting legitimate?

    • could use rule to never overwrite

    • but then conservative


However

However!

New rule: can overwrite a 0 or 1 with a *, but never overwrite a * with a 0 or 1

*

d

b

1*

0

1*

e

0

a2

c

1

0

a

a1

1

0

0

1

(a=1 implications above the lines and a=0 implications below the lines)

implies that a2 s-a-0 redundant


Combinational algorithm

Combinational Algorithm

redundancy_remove(G = (V,E))

while (there is unvisited n)

{

S1 = learn_implications(n = 1)

S0 = learn_implications(n = 0)

Forevery implication (l = v) in R {set l = constant v}

propagate constants

simplify network

}

v in {0,1}

This requires the set of redundancies R is compatible


Combinational algorithm1

Combinational Algorithm

learn_implications( G = (V,E), A)

forall (n = v in A) {label nv }

{

while (some rule can be invoked) {

let (n = b) be the new implication from rule

if (b = *) label n b ; continue

if (b conflicts with a current label)

return { l = * | l in E} // assumption A was inconsistent

elsen  b (I think we need to make sure a current label is not *)

}

return set of all current labels

}

A conflict is if the label is both 0 and 1.


Rules and properties

Rules and properties

  • At all times a net has a unique label

  • A 0 or 1 can be overwritten by a *

  • But a * is not allowed to be overwritten by a 0 or 1

  • Set R is a set of compatible redundancies


Key concept to prove that set of redundancies returned is compatible

Key concept to prove that set of redundancies returned is compatible

Implication Graph

  • Vertices are labeled with (n = r) for some net n and r in {0,1,*}

  • Root vertices labeled with (m=a) in A

  • There is exactly on leaf vertex

  • For non-root node its label can be obtained from the labeling of its parents by using one of the rules of inference.


Example implication graph

n8=1

n2=1

n1=1

n6=1

n5=0

n3=0

n4=1

n7=1

n9=1

Example - implication graph

n1

n7

n3

n4

n9

n8

n2

n5

n6


Key lemma

Key Lemma

Lemma: Let A be consistent. If a label (m = a) is overwritten by the label (m = *) in the current set of labels, then for all labels (nj= bj), there is an implication graph such that (m = a) is not a label of any vertex in the graph

Proof: it is proved that if a constant label is overwritten with a *, then every other label must have an implication graph which does not depend on the overwritten label.


Proof

nk

ni

nk

nk

nk

nk

nk

ni-1

ni

nk

ni-1

ni

ni

ni

ni

ni

ni-1

ni-1

ni-1

ni-1

ni-1

0

*

*

*

1

1

1

1

0

0

Proof.

Suppose m = a was first instance of overwritten by a * and let nj = bj be an implication that uses m=a: n1=b1n2=b2…m=a…nj=bjbut does not have a valid implementation graph now.ith

Case 1: 2: 3:

Case1. assume bj a constant. Then all bk are constants since a * can only imply a *.

OR


Theorems

Theorems

  • Let A be consistent. Then the set of labels returned by the algorithm is compatible.

  • Let nis-a-vi redundant for all be the set of redundant faults reported by the algorithm. Then the circuit obtained by setting ni = vi for all is combinationally equivalent to the original.


Sequential redundancies

Sequential Redundancies

  • We will use the notion of c-cycle replacement, which says that we are willing to wait c cycles after power-up to start getting the correct results

  • Every signal will have a superscript which gives a time frame relative to a generic one t, e.g. dt, dt+1, dt-2

  • Rules of implication are the same except when the implication is across a latch, the superscript is adjusted accordingly.


Example

at=0

et=0

ct+1=0

dt=0

bt+1=0

gt+1=0

at+1=0

et+1=0

ct+2=0

at=1

et=1

ct+1=1

dt=1

bt+1=1

gt+1=1

at+1=0

et+1=0

ct+2=0

Example

i

y

Might conclude that c=0 is a 2-cycle redundancy. But WRONG.

If we were to replace c by 0, and the new circuit powers-up in state 1 1, then it would produce x = 1 all the time. However old circuit produces x = 0 for t > 0.

f

d

b

a

g

e

c

Problem is that needed c=1 was needed when a=1 was used to imply c=0


New rule

at=1

et=1

ct+1=1

dt=1

bt+1=1

gt+1=1

at+1=0

et+1=0

ct+2=0

New Rule

Insure that no net is labeled with different values at different times.

Algorithm labels a net n with at most one value. If a net is labeled then we store a list of time offsets for when this label is valid.


C cycle redundncy

c-cycle redundncy

Definition: Suppose we conclude that n is s-a-v redundant at time t’

  • let t” be the least time offset in the implication graphs for n s-a-v such that some net m, mt’’ is labeled with a constant

  • then we say that n is c-cycle s-a-v redundancy where


Lemma 1

Lemma [1]

Let a net be c-cycle s-a-v redundant. Then the circuit obtained by setting net n = v results in a c-delayed safe replacement of the original circuit.

[1] M. Iyer, D. Long and M. Abramovici, “Identifying Sequential Redundancies without Search”, DAC 1996


Lemmas

Lemmas

Let A be a consistent assumption. If a label nt = a is replaced with nt = * in the current set of labels, then for all labels nt’j = bj, there is an implication graph such that nt= a is not a label in the graph.

Let A be a consistent assumption. Then the set of labels returned by the algorithm is compatible.


Theorem

Theorem

Let ni be ci-cycle s-a-vi redundant for all and . Then, the circuit obtained by setting the ni= vi for all i is an N-delay safe replacement of the original circuit.


Sequential redundancy removal w o state space exploration

Results: Application to sequential circuits - Table 2

10636

* full_simplify not run red = # redundancies removed

L = # latches, LR1, LR2 = # latches removed

A = mapped area after script.rugged, A1, A2 = mapped area after red. removals

C = c-cycle replacement (upper bound)

Compare to next table to see how much Sequential redundancy removal can to over combinational


Results application to combinational circuits

Results: Application to combinational circuits

10636

Combinational redundancy removal only


Question

Question

We saw that

  • Unroll the circuit n time frames

  • Assume that the present state lines in the first time frame are fully controllable

  • Assume that the next state lines in the last time frame are fully observable.

  • Use combinational test pattern generator

  • Two different procedures

    • Fault occurs only in the last time frame

    • Fault occurs in all time frames

  • In either case, lack of combinational test implies that fault is sequentially undetectable

    What can we say about c-cycle redundancy?


  • Questions

    Questions

    • How much did compatibility help in speeding up redundancy removal?

      • Seems like we can get the same set of redundancies without using compatibility.

    • Can we combine unrolling and compatible redundancies to get a more powerful method?

      • i.e. unroll and then reconnect registers after n time frames. Then detect and remove sequential redundancies.

    • Using the similarity with CODCs, can we extend the compatible redundancies to get a more powerful method?


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