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Reconfigurable Model-Based Test Program Generator for Microprocessors

RAS. ISP. Reconfigurable Model-Based Test Program Generator for Microprocessors. Alexander Kamkin , Eugene Kornykhin, and Dmitry Vorobyev {kamkin,kornevgen,vorobyev}@ispras.ru. Institute for System Programming of the Russian Academy of Sciences (ISPRAS) http://hardware.ispras.ru.

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Reconfigurable Model-Based Test Program Generator for Microprocessors

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  1. RAS ISP Reconfigurable Model-BasedTest Program Generator for Microprocessors Alexander Kamkin, Eugene Kornykhin, and Dmitry Vorobyev {kamkin,kornevgen,vorobyev}@ispras.ru Institute for System Programming of the Russian Academy of Sciences (ISPRAS) http://hardware.ispras.ru

  2. Levels of microprocessor verification Unit-level verification Core-level verification Model of a particular unit is tested Model of a microprocessor is tested as a whole via inputs and outputs signals with the help of test programs lui s1, 0xdead ori s1, s1, 0x0 lui s3, 0xbeef ori s3, s3, 0xf add v0, a0, a2 sub t1, t3, t5 add t7, s1, s3 A-MOST 2011: Advances in Model-Based Testing - March 20, 2011 - Berlin, Germany

  3. 0x2000: lui ... 0x2004: ori ... 0x2008: ori ... 0x200c: lui ... 0x2010: add ... 0x2014: sub ... 0x2018: add ... 0x2000: lui ... 0x2004: ori ... 0x2008: ori ... 0x200c: lui ... 0x2010: add ... 0x2014: sub ... 0x2018: add ... lui s1, 0xdead ori s1, s1, 0x0 lui s3, 0xbeef ori s3, s3, 0xf add v0, a0, a2 sub t1, t3, t5 add t7, s1, s3 Test programs-based verification Target design (RTL, FPGA) Execution traces (formatted text) Test programs (assembler, C) Trace comparator (Perl, C/C++) Reference simulator (C/C++, ADL) A-MOST 2011: Advances in Model-Based Testing - March 20, 2011 - Berlin, Germany

  4. IF ID EX WB lui s1, 0x2779 ori s1, s1, 0x0 lui s3, 0x4ee ori s3, s3, 0xf add v0, a0, a2 sub t1, t3, t5 add t7, s1, s3 IF ID EX WB Random Generation Template-Based Generation Approaches to test program construction v v Unformalized knowledge ? Design Requirements Test programs Advanced Model-Based Generation Advanced Model-Based Generation Manual Development  Formalized knowledge A-MOST 2011: Advances in Model-Based Testing - March 20, 2011 - Berlin, Germany

  5. Evolution of test program generators • Generator for a particular microprocessor • Model-based generator • Generation core • Microprocessor model • Architectural model • Test coverage model • Reconfigurable model-based generator • Generation core • Microprocessor description/configuration A-MOST 2011: Advances in Model-Based Testing - March 20, 2011 - Berlin, Germany

  6. Microprocessor model Generation core Testcoveragemodel General libraries Model-based test program generator Test program template Variable: addr = 0x100 Variable: reg Bias: Resource-Dependency(GPR) = 30 Bias: Alignment(4) = 50 Instruction: Load R5 <- ? Bias: Alignment(16) = 100 Repeat (addr < 0x200) Instruction: Store reg -> addr Select Instruction: Add ? <- reg + ? Bias: SumZero Instruction: Sub ? <- ? – ? addr = addr + 0x10 Generated test program Resource Initial Values: R6 = 8, R3 = – 25,..., R17 = – 16 100 = 7, 110 = 25,..., 1F0 = 16 Instructions: 500: Load R5 <- FF0 : 504: Store R4 -> 100 508: Sub R5 <- R6 – R4 50C: Store R4 -> 110 510: Add R6 <- R4 + R3 : 57C: Store R4 -> 1F0 580: Add R9 <- R4 + R17 Model-based test program generator Model Modeling engineer Engine Testtemplates Testtemplates Testtemplates Verification engineer Test programs Test programs Test programs A-MOST 2011: Advances in Model-Based Testing - March 20, 2011 - Berlin, Germany

  7. Microprocessor model Generation core Testcoveragemodel General libraries Reconfigurable test program generator Reconfigurable test program generator Model ADL translator Modeling engineer Specifications Engine Testtemplates Testtemplates Testtemplates Verification engineer Test programs Test programs Test programs A-MOST 2011: Advances in Model-Based Testing - March 20, 2011 - Berlin, Germany

  8. Goals of reconfigurable generators • There should be possibilities to easily change a microprocessor instruction set • add/remove microprocessor instructions • modify instructions’ semantics • Generator should implements facilities for changing microarchitectural properties • cache memory configuration • address translation algorithm • It should be able to generate test programs automatically according to high-level parameters A-MOST 2011: Advances in Model-Based Testing - March 20, 2011 - Berlin, Germany

  9. Design specification / configuration Instruction set specification (ADL language: nML/Sim-nML or other) Subsystems’ configuration (Subsystem-specific languages) ALU (Arithmetic) MMU (Memory) PCU (Pipeline) BPU (Branching) A-MOST 2011: Advances in Model-Based Testing - March 20, 2011 - Berlin, Germany

  10. Architectural description (nML/Sim-nML) Test program template ALU ?, ?, ? ADD R, ?, ? @ Default SUB ?, R, ? @ IntegerOverflow op ADD(rd: GPR, rs: GPR, rt: GPR) action = { if(NotWordValue(rs) || NotWordValue(rt))then UNPREDICTABLE(); endif; tmp_word = rs<31..31>::rs<31..0> + rs<31..31>::rt<31..0>; if(tmp_word<32..32> != tmp_word<31..31>)then SignalException("IntegerOverflow"); else rd = sign_extend(tmp_word<31..0>); endif; } syntax = format("add %s, %s, %s", rd.syntax, rs.syntax, rt.syntax) op ALU = ADD | SUB | ... precondition test situations equivalence classes A-MOST 2011: Advances in Model-Based Testing - March 20, 2011 - Berlin, Germany

  11. Memory configuration Buffer configuration buffer L1 { set = 4; length = 128; policy = LRU; line(tag:27, data:32); index(addr:36) = (addr[8:2]); match(addr:36) = (addr[35:9] == tag); } vAddr := sign_extend(offset) + base; if(vAddr<2..0> != 0)then SignalException("AddressError"); endif pAddr::CCA := AddressTranslation(vAddr, DATA, LOAD); memdata := LoadMemory(CCA, DWORD, pAddr, vAddr, DATA); rt := memdata; ... // AddressTranslation if(hit<TLB>(vAddr){loaded:PFN})then pAddr := PFN::vAddr<12..0>; ... // LoadMemory if(hit<L1>(pAddr){loaded:memdata})then rt := memdoubleword; ... Test program template LD ?, ?(?) @ hit<TLB>{loaded:PFN1} && miss<L1> && hit<L2> ... SD ?, ?(?) @ hit<TLB>{loaded:PFN2} && PFN1 = PFN2 && hit<L1> A-MOST 2011: Advances in Model-Based Testing - March 20, 2011 - Berlin, Germany

  12. Pipeline configuration pipeline() { IF(I); ID(I); EX(I); MEM(I); WR(I); } ... stageEX(I: Instruction) { switch(I.type) f case ALU: EX_ALU(I); case FPU: EX_FPU(I); ... }} stage FPU(I: Instruction) throws Inexact, Overflow, Underflow { delay(10..15); } A-MOST 2011: Advances in Model-Based Testing - March 20, 2011 - Berlin, Germany

  13. Supported test generation techniques • Template-based test program generation • Random generation of test programs • Combinatorial test program generation • Combinations of instructions, test situations, etc. • Combinations of pipeline hazards, exceptions, etc. • Combinations of branching instructions, traces, etc. A-MOST 2011: Advances in Model-Based Testing - March 20, 2011 - Berlin, Germany

  14. move b, 0x4 move t, 0 store t, (b) move c, 1 load a, (b) add c, a, d move f, 0x4 load e, (f) move t, 2 store t, (f) move g, 0xd bne c, g, error ... Structure of test programs … initialization test situation test case test action register dependency address dependency test oracle … A-MOST 2011: Advances in Model-Based Testing - March 20, 2011 - Berlin, Germany

  15. move b, 0x4 move t, 0 store t, (b) add ... ... ... move c, 1 sub load a, (b) load ?, (?) move f, 0x4 load lui s1, 0xdead ori s1, s1, 0x0 lui s3, 0xbeef ori s3, s3, 0xf add v0, a0, a2 sub t1, t3, t5 add t7, s1, s3 add ?, ?, ? add c, a, d store move t, 2 load ?, (?) load e, (f) store t, (b) Combinatorial generation scheme Testprogram normal overflow  cache hit cache miss  register dependency address dependency cache miss normal generation parameters cache hit address dependency register dependency A-MOST 2011: Advances in Model-Based Testing - March 20, 2011 - Berlin, Germany

  16. Data hazards ADD R, ?, ? ... SUB ?, R, ? Exceptions Data IF IF IF ID ID ID ME ME ME EX EX EX WR WR WR Structural hazards DIV.D ?, ?, ? ... MUL.S ?, ?, ? Branches Microprocessor pipeline hazards A-MOST 2011: Advances in Model-Based Testing - March 20, 2011 - Berlin, Germany

  17. Composition of pipeline hazards Composed template T1[T2 >> T3] · T4 // Template T1 (Memory dependency) LD ?, ?(?) @ hit<TLB>{loaded:PFN1} // Template T2 (Register dependency) ADD R, ?, ? // Template T3 (Structural hazard) DIV.S ?, ?, ? SUB ?, R, ? DIV.D ?, ?, ? SD ?, ?(?) @ hit<TLB>{loaded:PFN2} && PFN1 = PFN2 // Template T4 (Exception) FPU ?, ?, ? @ Overflow • Concatenation of templates (T1· T2) • Overlapping of templates (T1 || T2) • Nesting of a template (T1[T2]) • Shift of templates (T1 >> T2) A-MOST 2011: Advances in Model-Based Testing - March 20, 2011 - Berlin, Germany

  18. Generating test programs with branches INIT: ORI R1, R0, 2010 ORI R2, R0, 2011 // R1 != R2 ... J START NOP ... BACK: ADDI R1, R1, 1 // Control instruction FPU ?, ?, ? START: ... BEQ R1, R2, STOP LD ?, ?(?) J BACK NOP STOP: INIT ... BACK START ... BEQ J @ {false, true} STOP A-MOST 2011: Advances in Model-Based Testing - March 20, 2011 - Berlin, Germany

  19. MicroTESK test program generator A-MOST 2011: Advances in Model-Based Testing - March 20, 2011 - Berlin, Germany

  20. Case studies • Memory subsystem • MIPS64 microprocessor • DSP co-processor • Floating-point co-processors • DMA controller • Branch prediction unit A-MOST 2011: Advances in Model-Based Testing - March 20, 2011 - Berlin, Germany

  21. Some statistics Many critical bugs were found in the designs, which had been verified by hand-written, random-generated, and template-based test programs A-MOST 2011: Advances in Model-Based Testing - March 20, 2011 - Berlin, Germany

  22. Conclusion • Adapting the model-based testing approach for verification engineers • Domain-oriented languages • Handling frequent design changes & maintenance of the models • Easy-to-modify specifications / configurations • Bush-button test generation techniques A-MOST 2011: Advances in Model-Based Testing - March 20, 2011 - Berlin, Germany

  23. Contacts • Institute for System Programming of RAS (ISPRAS)http://www.ispras.ru • Hardware Verification R&D @ ISPRAShttp://hardware.ispras.ru • Alexander Kamkinkamkin@ispras.ru A-MOST 2011: Advances in Model-Based Testing - March 20, 2011 - Berlin, Germany

  24. Thank You!Questions? A-MOST 2011: Advances in Model-Based Testing - March 20, 2011 - Berlin, Germany

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