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Design of a 4 Bit ALU EE166 Project Jing Li, Justin Lei, Xuemei Liu Advisor: Dr. David Parent Date: 12/05/2005

Design of a 4 Bit ALU EE166 Project Jing Li, Justin Lei, Xuemei Liu Advisor: Dr. David Parent Date: 12/05/2005. Content. Abstract Introduction Arithmetic Unit Mux-Based D-Flip Flop Logic Unit 4-bit ALU Layout and Verification Conclusion. Abstract.

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Design of a 4 Bit ALU EE166 Project Jing Li, Justin Lei, Xuemei Liu Advisor: Dr. David Parent Date: 12/05/2005

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  1. Design of a 4 Bit ALUEE166 Project Jing Li, Justin Lei, Xuemei LiuAdvisor: Dr. David ParentDate: 12/05/2005 EE166 Project – 4-Bit ALUJ. Li J. Lei X.M. Liu

  2. Content • Abstract • Introduction • Arithmetic Unit • Mux-Based D-Flip Flop • Logic Unit • 4-bit ALU Layout and Verification • Conclusion EE166 Project – 4-Bit ALUJ. Li J. Lei X.M. Liu

  3. Abstract • Goal- To design a 4-bit ALU which has: - 4 logic functions (AND, OR, NOT, and XOR), - 8 arithmetic functions (A+B, A+B’, A+1, A-1, A+B+1, Transfer A, A+B’+1) • Specification: - Clock speed 200 MHz - Load 35fF - Area 370um X450um - Power 17mWatts EE166 Project – 4-Bit ALUJ. Li J. Lei X.M. Liu

  4. Introduction This 4-bit ALU consists of four parts: Y-Generator, Full Adder, 2 to 1 Mux, Logical Unit A0 A1 A2 A3 B0 B1 B2 B3 C Arithmetic Unit Cout SUM0 SUM1 SUM2 SUM3 Y-Gen Full Adder 2 to 1 MUX Logic Unit M S0 S1 EE166 Project – 4-Bit ALUJ. Li J. Lei X.M. Liu

  5. M S1 S0 Carry In Function 0 0 0 0 TransferA  0 0 0 1 A + 1  0 0 1 0 A + B 0 0 1 1 A + B + 1  0 1 0 0 A + B’ 0 1 0 1 A + B’ +1 0 1 1 0 A - 1 0 1 1 1  TransferA 1 0 0 X  A XOR B 1 0 1 X A OR B  1 1 0 X A AND B 1 1 1 X  NOT A Function Table A, B = 4 Bit Input, X = don’t care Condition M , S0, S1 = Status Control Pin EE166 Project – 4-Bit ALUJ. Li J. Lei X.M. Liu

  6. Logic Function NC Verilog Verification EE166 Project – 4-Bit ALUJ. Li J. Lei X.M. Liu

  7. Arithmetic Function NC Verilog Verification EE166 Project – 4-Bit ALUJ. Li J. Lei X.M. Liu

  8. Longest Path Calculation Τphl = 5ns / (14 + 4) = 5ns / 18 = 0.277 ns Considering AOI has long delay time, I steal time from inverter and give it to AOI. EE166 Project – 4-Bit ALUJ. Li J. Lei X.M. Liu

  9. After Spice Simulation Size EE166 Project – 4-Bit ALUJ. Li J. Lei X.M. Liu

  10. Full Adder Schematic Cout = AB+AC+BC SUM= A + B + C We use two AOI implement full adder, because it gives small area and nice delay. EE166 Project – 4-Bit ALUJ. Li J. Lei X.M. Liu

  11. 4Bit Adder Test Bench In our project the most important long path is ripple adder, so I connect all A to high, B to low, and toggle Cin to test the worst case of 4 Bit adder. EE166 Project – 4-Bit ALUJ. Li J. Lei X.M. Liu

  12. 4Bit Adder Test Result Calculated delay time:τplh= 2.4ns τphl=2.4ns Test delay time:τplh= 2.27ns τphl=2.11ns EE166 Project – 4-Bit ALUJ. Li J. Lei X.M. Liu

  13. Adder Layout & LVS EE166 Project – 4-Bit ALUJ. Li J. Lei X.M. Liu

  14. Mux-based D Flip Flopschematic EE166 Project – 4-Bit ALUJ. Li J. Lei X.M. Liu

  15. DFF Holdtime Holdtime_Fall Holdtime_rise Design: holdtime fall Measured value Design: holdtime rise Measured value: 0.65ns 0.52ns 0.65ns 0.47ns EE166 Project – 4-Bit ALUJ. Li J. Lei X.M. Liu

  16. DFF Setup-time Design setup_falltime: 0.65ns Measured: 0.436ns Design setup_risetime:0.65ns Measured: 0.57ns EE166 Project – 4-Bit ALUJ. Li J. Lei X.M. Liu

  17. D Flip Flop-layout NAND Keeper muxes Wn: 8.99um Wp: 7.92um Wn: 6.49um Wp: 11.2um Wn & Wp : 8um & 4.85um Wn: 7.62um Wp:6.71um Wn & Wp :1.5 um Wn:8.37um Wp: 14. 5um EE166 Project – 4-Bit ALUJ. Li J. Lei X.M. Liu

  18. DFF LVS EE166 Project – 4-Bit ALUJ. Li J. Lei X.M. Liu

  19. 2-to-1 MUX Schematic and Layout Schematic Layout EE166 Project – 4-Bit ALUJ. Li J. Lei X.M. Liu

  20. Logic Unit F = S1’AB+S0AB’+S0A’B+S1S0’A’ Schematic AND OR NOT XOR EE166 Project – 4-Bit ALUJ. Li J. Lei X.M. Liu

  21. Logic Unit --- test bench Transient response Test bench To test the worst case delay, toggle S0, set A,B low, S1 high Target delay: 1ns measured value: 0.9ns EE166 Project – 4-Bit ALUJ. Li J. Lei X.M. Liu

  22. Logic Unit---Layout & LVS Layout EE166 Project – 4-Bit ALUJ. Li J. Lei X.M. Liu

  23. Y-Generator Truth table Y = BS0 + B’S1 b a Y-GEN S1 S0 C in Full-adder C_out Sum EE166 Project – 4-Bit ALUJ. Li J. Lei X.M. Liu

  24. Y-Gen Schematic & Layout Layout Schematic EE166 Project – 4-Bit ALUJ. Li J. Lei X.M. Liu

  25. 4-Bit ALU Top Level Schematic EE166 Project – 4-Bit ALUJ. Li J. Lei X.M. Liu

  26. 4-Bit ALU Layout & LVS EE166 Project – 4-Bit ALUJ. Li J. Lei X.M. Liu

  27. 4-Bit ALU Test Bench Critical path exists between B0 and F3 S0, S1, and M are set at the addition mode Set A3A2A1A0 = 0111, B3B2B1 = 100, toggle B0, test F3 EE166 Project – 4-Bit ALUJ. Li J. Lei X.M. Liu

  28. 4-Bit ALU Post Extraction Simulation EE166 Project – 4-Bit ALUJ. Li J. Lei X.M. Liu

  29. 4-Bit ALU Power Power Consumption: 17mw EE166 Project – 4-Bit ALUJ. Li J. Lei X.M. Liu

  30. Conclusion • Our designed 4-bit ALU met the pre-defined specification --- Speed 200 Mhz --- Power consumption 17m Watts --- Area 370um X450um • Work hours more than 100 hours • Learned from each other through teamwork EE166 Project – 4-Bit ALUJ. Li J. Lei X.M. Liu

  31. Acknowledgments • Many thanks toProfessor David Parent for his guidance • Thanks to Cadence Design System EE166 Project – 4-Bit ALUJ. Li J. Lei X.M. Liu

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