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Robust FPGA Resynthesis Based on Fault-Tolerant Boolean Matching

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Robust FPGA Resynthesis Based on Fault-Tolerant Boolean Matching

Yu Hu1, Zhe Feng1, Lei He1 and Rupak Majumdar2

1Electrical Engineering Dept., UCLA

2Computer Science Dept., UCLA

Presented by Yu Hu

Address comments to [email protected]

- Background and Motivation
- Preliminaries
- Robust Resynthesis Algorithms
- Experimental Results
- Conclusion and Future Work

- Late CMOS scaling reduces device reliability
- Single event upset (SEU) due to cosmic rays
- Affects configuration SRAM cells in FPGAs
- Permanent soft error rate (SER)
- Need rewriting SRAM for recovery

- Affects combinational circuits and FFs
- Transient SER
- Can be recovered in multiple clock cycles

- Affects configuration SRAM cells in FPGAs

Our work

Low-cost, complementary approach to existing techniques!

[A. Djupdal and P. Haddow, Yield Enhancing Defect Tolerance Techniques for FPGAs, MAPLD 2006]

- Stochastic synthesis assumes probabilistic logic values to model effect of random defects
- Break the conventional Boolean view which assumes deterministic Boolean ‘0’ and ‘1’ values

- Key to stochastic synthesis: Logic Masking

Masked faults

0

1

- Stochastic Synthesisintelligently places logic masking.
- Logic Masking reduces the probability of the propagation of random faults
- Maximizes the stochastic yield

- However, logic synthesis to maximize yield rate w/o explicit redundancy and testing has not been studied for fault tolerance!
- Key questions
- How much does logic masking affect robustness?
- How and where to place logic masking?

Different synthesis leads to different logic masking.

Stochastic synthesis maximizes logic masking!

18 synthesis solutions obtained by Berkeley ABC

(for MCNC i10, LUT bit fault rate = 0.1%)

- Propose a Robust FPGA resynthesis (ROSE)
- Maximize the stochastic yield rate for FPGAs
- No need to locate faults
- Use the same synthesis for different chips of one FPGA application

- Proposed a new PLB template for robustness
- ROSE + Robust Template reduces fault rate by 25% with 1% fewer LUTs, and increases MTBF by 31% while preserving the logic depth
- compared to Berkeley ABC

- Background
- Preliminaries
- Robust Resynthesis
- Experimental Results
- Conclusion and Future Work

- Attempt to re-map a logic block by Boolean matching
- Boolean matching can be used to handle both homogenous and heterogeneous PLBs

- Multi-iterations of Boolean Matching-based Resynthesis

(Source: Andrew Ling, University of Toronto, DAC'05)

2-LUT

f

g

2-LUT

2-LUT

2-LUT

?

2-LUT

- Formulate the sub-problem of resynthesis to Boolean matching (BM)
- BM: Can function fbe implemented in circuit g ?
- Resynthesis: Is there a configuration to gso that for all inputs to g, f is equivalent to g?

- Existing algorithms: area/delay-optimal

(Source: Andrew Ling, University of Toronto, DAC'05)

- Background
- Preliminaries
- Robust Resynthesis
- Problem Formulation
- FTBM Algorithm
- Robust PLB Template

- Experimental Results
- Conclusion and Future Work

- Model both faults in LUT configurations and the faults in intermediate wires as random variables, whose probabilities are given as inputs of our problem.

- Boolean Matching
- Inputs
- PLB H and Boolean function F
- Fault rates for the inputs and the SRAM bits of the PLB

- Outputs
- Either that F cannot be implemented by PLB H
- Or the configuration of Hwhich minimizes the probability that the faults are observable in the output of the PLB under all input vectors.

- FTBM tasks breakdown:
- Step 1: Find a Boolean matching solution
- Step 2: Evaluation the stochastic fault rate of a solution

- Inputs

- Fault-Tolerant Boolean Matching

Conjunctive Normal Form (CNF)

- If implementable, multiple configurations might exist
- The one with minimal fault rate is needed!

Stochastic SAT

Deterministic SAT

Deterministic SAT vs. SSAT

- Simulation-based fault rate calculation
- Not scalable for multiple defects

- SAT-based fault rate calculation
- Intelligently modeling random defects

GUI Version 1

Binary search is performed to find the maximal β

Faults in intermediate wires

Faults in LUT configurations

Boolean matching

g= !x1!x3+ !x2

PLB Template

Boolean function

PLB Characteristic Function:G = G LUT1 ·G LUT2 · G LUT3

G LUT = ( x1 + x2+ ¬L0 + z) ( x1 + x2+ L0 + ¬ z)

( x1 + ¬x2+ ¬L1 + z) ( x1 + ¬x2+ L1 + ¬ z)

(¬x1 + x2+ ¬L2 + z) (¬x1 + x2+ L2 + ¬ z)

(¬x1 + ¬x2+ ¬L3 + z) (¬x1 + ¬x2+ L3 + ¬ z)

SAT Instance:

G expand = G[X/000, f/1, z/z0] · G[X/001, f/1, z/z1]

G[X/010, f/1, z/z2] · G[X/011, f/0, z/z3]

G[X/100, f/1, z/z4] · G[X/101, f/1, z/z5]

G[X/110, f/0, z/z6] · G[X/111, f/0, z/z7]

G = G LUT1 ·G LUT2· G LUT3

Replication

SAT Instance:

G expand = G[X/000, f/1, z/z0] · G[X/001, f/1, z/z1]

G[X/010, f/1, z/z2] · G[X/011, f/0, z/z3]

G[X/100, f/1, z/z4] · G[X/101, f/1, z/z5]

G[X/110, f/0, z/z6] · G[X/111, f/0, z/z7]

Returned SAT assignments: L1(00) = 0, L1(01)=0, L1(10)=0, L1(11)=1, …

SAT!

¬ (L1(00) = 0, L1(01)=0, L1(10)=0, L1(11)=1, …)

/* Complement of previous SAT assignments */

Augmented SAT Instance:

G expand = G[X/000, f/1, z/z0] · G[X/001, f/1, z/z1]

G[X/010, f/1, z/z2] · G[X/011, f/0, z/z3]

G[X/100, f/1, z/z4] · G[X/101, f/1, z/z5]

G[X/110, f/0, z/z6] · G[X/111, f/0, z/z7]

New Configuration

Previous Configuration

Fault rate = 0.2

Fault rate = 0.3

- Area efficient templates [A. Ling, DAC’05]
- Proposed robust template w/ path-reconvergence
- Can be configured by existing FPGAs

- Robust PLB template introduces more potential of don’t-cares
- ROSE maximizes don’t-cares iteratively at each template output

Observability don’t-care

Satisfiability don’t-care

- Background
- Preliminaries
- Robust Resynthesis
- Experimental Results
- Conclusion and Future Work

- Implementation in OAGear
- SAT-BM uses miniSAT2.0

- QUIP benchmarks are tested
- Are first mapped with 4-LUTs by Berkeley ABC

- Resynthesis settings
- One traversal is performed
- Blocks with up to 10 inputs are considered

- The fault rate of the chip is calculated by Monte Carlo simulation with 20K random vectors assuming the single fault
- Results are verified by ABC equivalency checkers

>30% fault rate reduction!

- Fault rate is the percentage of input vectors that cause observable output errors assuming the single fault.

ABC vs. ROSE/A vs. ROSE/R:

1: 0.9 : 0.99

31% MTBF increase!

- SER modeling: [Mukherjee, HPCA, 2005]
- Assume max-size FPGA: 330,000 LUTs

- Background
- Preliminaries
- Robust Resynthesis
- Experimental Results
- Conclusion and Future Work

- Developed ROSE and a robust template.
- ROSE is an orthogonal approach compared to existing fault-tolerant technique.
- Virtually no overhead on power, delay and area

- In the future, we will consider
- Multiple correlated faults,
- Alternative algorithms,
- Extension to standard cell-based circuits,
- Impacts on testability.

Robust FPGA Resynthesis Based on Fault-Tolerant Boolean Matching

Yu Hu, Zhe Feng, Rupak Majumdar and Lei He

University of California, Los Angeles