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Digital Electronics Principles & Applications Seventh Edition. Roger L. Tokheim. Chapter 7 Flip-Flops. ©2008 The McGraw-Hill Companies, Inc. All rights reserved. INTRODUCTION. Combinational vs. Sequential Logic Circuits R-S Flip-flop Clocked R-S Flip-flop D Flip-flop J-K Flip-flop

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Digital Electronics

Principles & Applications

Seventh Edition

Roger L. Tokheim

Chapter 7

Flip-Flops

©2008 The McGraw-Hill Companies, Inc. All rights reserved.


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INTRODUCTION

Combinational vs. Sequential Logic Circuits

R-S Flip-flop

Clocked R-S Flip-flop

D Flip-flop

J-K Flip-flop

Latches (simple memory devices)

Triggering of flip-flops

Schmitt triggered device


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Logic Circuits

Logic circuits are classified into two groups:

Combinational Logic Circuits

Basic building

blocks include:

Sequential Logic Circuits

Basic building blocks

include FLIP-FLOPS:


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QUIZ

1. Basic building blocks for __________ (combinational, sequential) logic circuits include logic gates (such as NOT, AND, and OR).

combinational

2. Basic building blocks for sequential logic circuits include various flip-flops. (True or False)

True

3. A flip-flop is an example of a device used in __________ (combinational, sequential) logic circuits.

sequential


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Set

Normal

S

Q

FF

R

Q

Reset

Comple-mentary

Mode of OperationInputsOutputs

S R Q Q’

Prohibited0 0 1 1

Set0 1 1 0

Reset1 0 0 1

Hold1 1 Q Q’

NOTE: Active-LOW inputs

R-S Flip-Flop

Symbols:

Truth Table:


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L

?

H

Mode of operation = ?

H

?

H

Mode of operation = ?

H

?

L

Mode of operation = ?

QUIZ

What is the mode of operation of the R-S flip-flop (set, reset or hold)?

What is the output at Q from the R-S flip-flop (active LOW inputs)?

High

Set

High

Hold

Low

Reset


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Set

FF

Normal

S

Q

Clock

CLK

Q

Reset

R

Comple-mentary

Clocked R-S Flip-Flop

Symbols:

Truth Table:

Mode of operationInputsOutputs

Clk S R Q Q’

Hold+ pulse 0 0 no change

Reset+ pulse 0 1 0 1

Set + pulse 1 0 1 0

Prohibited 1 1 1 1

NOTE: Active-High inputs


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H

^

L

?

Mode of operation = ?

L

^

L

?

Mode of operation = ?

L

^

H

?

Mode of operation = ?

QUIZ

What is the mode of operation of the clocked R-S flip-flop (set, reset, hold)?

What is the output at Q from the clocked R-S flip-flop (active HIGH inputs)?

High

Set

High

Hold

Low

Reset


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D Flip-Flop

Symbol:

(with asynchronous PS & CLR)

Truth Table:

Mode of Operation Inputs OutputsPS CLR CLK D Q Q’

Asynchronous set0 1 X X 1 0

Asynchronous reset1 0 X X 0 1

---------------------------------------------------------------------

Prohibited 1 1 X X 1 1

Set1 1 ^ 1 1 0

Reset 1 1 ^ 0 0 1

X = irrelevant

^ = L-to-H transition of the clock pulse


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L

H

^

H

?

Mode of operation = ?

H

L

^

H

?

Mode of operation = ?

H

H

^

H

?

Mode of operation = ?

What is the mode of operation of the D flip-flop?

What is the output at Q from the D flip-flop?

QUIZ

High

Asynchronous Set

Low

Reset

High

Set


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J-K Flip-Flop

Symbol:

Truth Table:

Mode of OperationInputsOutputs

PS Clr Clk J K Q Q’

Asynchronous set0 1 x x x 1 0

Asynchronous reset1 0 x x x 0 1

Prohibited 0 0 x x x 1 1

-------------------------------------------------------------------------

Hold 1 1 ^ 0 0 no change

Reset 1 1 ^ 0 1 0 1

Set1 1 ^ 1 0 1 0

Toggle 1 1 ^ 1 1 opposite

x = Irrelevant

^ = H-to-L transition of clock pulse


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L

L

^

H

H

H

H

^

H

H

?

?

Mode of

operation = ?

Mode of

operation = ?

H

H

^

H

H

H

H

^

H

H

?

?

Mode of

operation =?

Mode of

operation = ?

H

L

^

H

H

H

H

^

H

L

?

?

Mode of

operation = ?

Mode of

operation = ?

What is the mode of operation of the J-K flip-flop?

What is the output at Q from the J-K flip-flop?

QUIZ

High

High

Preset

Toggle

Low

Low

Toggle

Toggle

Low

Low

Reset

Clear


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Latch

  • A fundamental digital storage device

  • The act of storing data for a time, such as “to latch”

  • An R-S flip-flop is an example of a latch

  • A D flip-flop can perform as a latch

  • In IC form (examples: 4-bit, 8-bit, 9-bit, 10 bit)

  • Is commonly imbedded in complex ICs


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QUIZ

1. A fundamental digital storage device is sometime called a(n) ___ (gate, latch).

latch

2. The job of a latch can be performed by a(n) ___ (gate, D-flip-flop).

D-flip-flop

3. We say that “to latch” is the act of storing data for a time. (True or False)

True

4. Latches are commonly imbedded in more complex ICs and serve as temporary memory devices. (True or False)

True


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H

L

Negative-edge triggering

Positive-edge triggering

time

Level triggering

Triggering of Flip-Flops

  • Level-triggering is the transfer of data from input to output of a flip-flop anytime the clock pulse is HIGH.

  • Edge-triggering is the transfer of data from input to output of a flip-flop on the rising edge (L-to-H) or falling edge (H-to-L) of the clock pulse. Edge triggering may be either positive-edge (L-to-H) or negative-edge (H-to-L). Master-slave triggering is an older technique using the whole clock pulse but think of a master-slave flip-flop as having negative-edge triggering.


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H

L

C

B

A

time

QUIZ

1. If a flip-flop triggers on the L-to-H transition of the clock pulse (see A) it is called a __________ (level, positive-edge) triggered device.

positive-edge

2. If a flip-flop triggers on the H-to-L transition of the clock pulse (see B) it is called a __________ (level, negative-edge) triggered device.

negative-edge

3. If a flip-flop triggers while the clock pulse is HIGH (see C) it is called a __________ (level, positive-edge) triggered device.

level


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Schmitt Trigger Operation

Positive-going threshold

Negative-going threshold

Output

Input

Schmitt trigger device

“squares” up input


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QUIZ

1. The symbol at the lower right is that of a __________ (magneto-optical, Schmitt trigger) inverter.

Schmitt trigger

2. If the input signal to the Schmitt trigger inverter is a sine wave the output will be a __________ (square-wave, triangular-wave).

square wave

3. A Schmitt-trigger device will “digitize” or square up input signals with slow rise times and slow fall times. (True or False)

True


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REVIEW

Combinational vs. Sequential Logic Circuits

R-S Flip-flop

Clocked R-S Flip-flop

D Flip-flop

J-K Flip-flop

Latches (simple memory devices)

Triggering of flip-flops

Schmitt triggered device


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