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Russell Peak Senior Researcher Manufacturing Research Center Georgia Tech

2002 International Conference on Electronics Packaging (ICEP) JIEP/ IMAPS Japan, IEEE CPMT Japan Chapter Dai-ichi Hotel Seafort, Tokyo, Japan April 17-19, 2002.

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Russell Peak Senior Researcher Manufacturing Research Center Georgia Tech

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  1. 2002 International Conference on Electronics Packaging (ICEP) JIEP/ IMAPS Japan, IEEE CPMT Japan Chapter Dai-ichi Hotel Seafort, Tokyo, Japan April 17-19, 2002 Techniques and Tools for Product-Specific Analysis TemplatesTowards Enhanced CAD-CAE Interoperability for Simulation-Based Design and Related Topics http://eislab.gatech.edu/pubs/conferences/2002-jiep-icep-peak/ Russell Peak Senior Researcher Manufacturing Research Center Georgia Tech

  2. Abstracthttp://eislab.gatech.edu/pubs/conferences/2002-jiep-icep-peak/Abstracthttp://eislab.gatech.edu/pubs/conferences/2002-jiep-icep-peak/ Techniques and Tools for Product-Specific Analysis TemplatesTowards Enhanced CAD-CAE Interoperability for Simulation-Based Design and Related Topics Design engineers are becoming increasingly aware of “analysis template” pockets that exist in their product domain. For example, thermal resistance and interconnect reliability analysis are common templates for electronic chip packages, while tire-roadway templates exist to verify handling, durability, and slip requirements. Such templates may be captured as paper-based notes and design standards, as well as loosely structured spreadsheets and electronic workbooks. Often, however, they are not articulated in any persistent form. Some CAD/E software vendors are offering pre-packaged analysis template catalogs like the above; however, they are typically dependent on a specific toolset and do not present design-analysis idealization associativity to the user. Thus, it is difficult to adapt, extend, or transfer analysis template knowledge. As noted in places like the 2001 International Technology Roadmap for Semiconductors (ITRS), domain- and tool-independent techniques and related standards are necessary. This paper overviews infrastructure needs and emerging analysis template theory and methodology that addresses such issues. Patterns that naturally exist in between traditional CAD and CAE models are summarized, along with their embodiment in a knowledge representation known as constrained objects. Industrial applications for airframe structural analysis, circuit board thermomechanical analysis, and chip package thermal resistance analysis are noted. This approach enhances knowledge capture, modularity, and reusability, as well as improves automation (e.g., decreasing total simulation cycle time by 75%). The object patterns also identify where best to apply information technologies like STEP, XML, CORBA/SOAP, and web services. We believe further benefits are possible if these patterns are combined with other efforts to enable ubiquitous analysis template technology. Trends and needs towards this end are discussed, including analogies with electronics like JEDEC package standards and mechanical subsystems.

  3. Nomenclature

  4. Contents • Motivation • Introduction to Information Modeling and Knowledge Representation • Analysis Template Applications • International Collaboration on Engineering Frameworks • Recommended Solution Approach

  5. Motivation: Product ChallengesTrend towards complex multi-disciplinary systems Demanding End User Applications MEMS devices http://www.zuken.com/solutions_board.asp 3D interconnects Source: www.ansys.com

  6. Motivation: Engineering Tool Challenges2001 International Technology Roadmap for Semiconductors (ITRS)http://public.itrs.net/Files/2001ITRS/Home.htm • Design Sharing and Reuse • Tool interoperability • Standard IC information model • Integration of multi-vendor and internal design technology • Reduction of integration cost • Simulation module integration • Seamless integration of simulation modules • Interplay of modules to enhance design effectiveness

  7. Advances Needed in Engineering Frameworks2001 International Technology Roadmap for Semiconductors (ITRS)http://public.itrs.net/Files/2001ITRS/Home.htm

  8. AnalogyPhysical Integration Modules  Model Integration Frameworks Wafer Level Packaging RF, Digital, Analog, Optical, MEMS Design System Architecture Stacked Fine-Pitch BGA www.shinko.co.jp System-On-a-Package (SOP) www.prc.gatech.edu 2001 ITRS Multidisciplinary challenges require innovative solution approaches

  9. Interoperability Seamless communication between people, their models, and their tools. • Requires techniques beyond traditional engineering • Information models • Abstract data types • Object-oriented languages (UML, STEP Express, …) • Knowledge representation • Constraint graphs, rules, … • Web/Internet computing • Middleware, agents, mobility, … • Emerging field: engineering information methods • Analogous to CAD and FEA methods

  10. Contents • Motivation • Introduction to Information Modeling and Knowledge Representation • Analysis Template Applications • International Collaboration on Engineering Frameworks • Recommended Solution Approach

  11. “Collaborative Modeling” vs. “Tool Usage” Existing Tools Tool A1 Tool An ... Content Coverage Gaps Product Model - integrated information model - knowledge representation Integration Gaps

  12. Example Information Model in Express (ISO 10303-11) spring system tutorial SCHEMA spring_systems; ENTITY spring; undeformed_length : REAL; spring_constant : REAL; start : REAL; end0 : REAL; length0 : REAL; total_elongation : REAL; force : REAL; END_ENTITY; ENTITY two_spring_system; spring1 : spring; spring2 : spring; deformation1 : REAL; deformation2 : REAL; load : REAL; END_ENTITY; END_SCHEMA;

  13. Instance Model and Example Applicationspring system tutorial Fragment from an instance model - (a.k.a. Part 21 “STEP File” - ISO 10303-21) #1=TWO_SPRING_SYSTEM(#2,#3,1.81,3.48,10.0); #2=SPRING(8.0,5.5,0.0,9.81,9.81,1.81,10.0); #3=SPRING(8.0,6.0,9.8,19.48,9.66,1.66,10.0);

  14. PWB Stackup Design & Analysis Tool

  15. Application-Oriented Information Model - Express-G notation PWB Stackup Design & Analysis Tool

  16. Contents • Motivation • Introduction to Information Modeling and Knowledge Representation • Analysis Template Applications • International Collaboration on Engineering Frameworks • Recommended Solution Approach

  17. Analysis Template Catalog:Chip Package Simulationthermal, hydro(moisture), fluid dynamics(molding), mechanical and electrical behaviors • PakSi-TM and PakSi-E tools http://www.icepak.com/prod/paksi/ as of 10/2001 • Chip package-specific behaviors: thermal resistance, popcorning, die cracking, delaminating, warpage & coplanarity, solder joint fatigue, molding, parasitic parameters extraction, and signal integrity

  18. Analysis Template Methodology & X-Analysis Integration Objectives (X=Design, Mfg., etc.) • Goal: Improve engineering processes via analysis templates with enhanced CAx-CAE interoperability • Challenges (Gaps): • Idealizations & Heterogeneous Transformations • Diversity: Information, Behaviors, Disciplines, Fidelity, Feature Levels, CAD/CAE Methods & Tools, … • Multi-Directional Associativity: DesignAnalysis, Analysis  Analysis • Focus: Capture analysis template knowledge for modular, regular design usage • Approach: Multi-Representation Architecture (MRA)using Constrained Objects (COBs)

  19. X-Analysis Integration Techniquesfor CAD-CAE Interoperabilityhttp://eislab.gatech.edu/tools/XaiTools/ a. Multi-Representation Architecture (MRA) b. Explicit Design-Analysis Associativity c. Analysis Module Creation Methodology

  20. COB-based Constraint Schematic for Multi-Fidelity CAD-CAE InteroperabilityFlap Link Benchmark Example

  21. An Introduction to X-Analysis Integration (XAI)Short Course Outline Part 1: Constrained Objects (COBs) Primer • Nomenclature Part 2: Multi-Representation Architecture (MRA) Primer • Analysis Integration Challenges • Overview of COB-based XAI Part 3: Example Applications • Airframe Structural Analysis (Boeing) • Circuit Board Thermomechanical Analysis (DoD, JPL/NASA) • Chip Package Thermal Analysis (Shinko) • Summary Part 4: Advanced Topics & Current Research

  22. Chip Package Products Shinko Quad Flat Packs (QFPs) Plastic Ball Grid Array (PBGA) Packages

  23. Flexible High Diversity Design-Analysis Integration Electronic Packaging Examples: Chip Packages/Mounting Shinko Electric Project: Phase 1 (completed 9/00) Design Tools Modular, Reusable Template Libraries Analysis Modules (CBAMs) of Diverse Behavior & Fidelity Prelim/APM Design Tool Analysis Tools XaiTools ChipPackage XaiTools ChipPackage General Math Mathematica FEAAnsys Thermal Resistance Analyzable Product Model 3D XaiTools PWB DB Materials DB* ThermalStress EBGA, PBGA, QFP Basic 3D** Basic Documentation Automation AuthoringMS Excel ** = Demonstration module

  24. COB-based Analysis TemplateTypical Highly Automated Results COB = constrained object Analysis Module Tool Auto-Created FEA Inputs (for Mesh Model) FEA Temperature Distribution Thermal Resistance vs. Air Flow Velocity

  25. Pilot & Initial Production Usage ResultsProduct Model-Driven Analysis VTMB = variable topology multi-body technique [Koo, 2000] • Reduced FEA modeling time > 10:1 (days/hours  minutes) • Reduced simulation cycle > 75% References [1] Shinko 5/00 (in Koo, 2000) [2] Shinko evaluation 10/12/00 • Enables greater analysis intensity  Better designs • Leverages XAI / CAD-CAE interoperability techniques • Objects, Internet/web services, ubiquitization methodology, …

  26. Analysis Template Merits • Provides methodology for bridging associativity gap • Multi-representation architecture (MRA) & constrained objects (COBs): • Address fundamental issues • Explicit CAD-CAE associativity:multi-fidelity, multi-directional, fine-grained • Enable analysis template methodology  Flexibility & broad application • Increase quality, reduce costs, decrease time (ex. 75%): • Capture engineering knowledge in a reusable form • Reduce information inconsistencies • Increase analysis intensity & effectiveness

  27. Contents • Motivation • Introduction to Information Modeling and Knowledge Representation • Analysis Template Applications • International Collaboration on Engineering Frameworks • Recommended Solution Approach

  28. Towards Greater Standards-Based InteroperabilityTarget Analogy with Electronics Systems Middleware Generic Geometric Modeling Tools, Math Tools, FEA Tools, Requirements & Function Tools, … Product-Specific Simulation-Based Design Tools APMs CBAMs Extended MRA ABBs Linkages to Other Life Cycle Models SMMs • Today: - Monolithic software applications; Few interchangeable “parts” • Next Steps: - Identify other formal patterns and use cases (natural subsystems / levels of “packaging”) - Define standard architectures and interfaces among subsystems

  29. 2002 NASA-ESA Workshop on Aerospace Product Data Exchange ESA/ESTEC, Noordwijk (ZH), The Netherlands April 9-12, 2002 ISO 10303 series Progress on Standards-Based Engineering Frameworks that include STEP AP210 (Electronics), PDM Schema, and AP233 (Systems)An Engineering Framework Interest Group (EFWIG) Overview Russell Peak - Georgia Tech, Atlanta GA, USA Mike Dickerson - JPL/NASA, Pasadena CA, USA Lothar Klein - LKSoft, Kuenzell, Germany Steve Waterbury - NASA-Goddard, Greenbelt MD, USA Greg Smith - Boeing, Seattle WA, USA Tom Thurman - Rockwell Collins, Cedar Rapids IA, USA Jim U'Ren - JPL/NASA, Pasadena CA, USA Ken Buchanan - ATI/PDES Inc., Charleston SC, USA

  30. Scope of Engineering Framework Interest Group A PDES Inc. Systems Engineering Subprojecthttp://eislab.gatech.edu/efwig/ • Interoperability in multi-disciplinary engineering development environments • Emphasis dimensions: • Organizational Level: engineering group/department • Domains: systems & s/w engineering, electromechanical, analysis • Design stages: WIP designs at concept, preliminary, and detailed stages • Awareness of design interfaces to other life cycle phases: • pursuit & order capture, mfg., operation/service, and disposal An international consortium for standards-based collaborative engineering http://pdesinc.aticorp.org/

  31. What is the context of Systems Engineering? User/Owner/Operator Management Marketing BusinessStrategy Concept RFP Contract Proposal Management Info Management Info Digital Electrical Controls Logistics Software Chemical Mechanical Civil Communications Maintenance Manufacture User/Owner/Operator Acquisition Authority Systems Engineering Specifications STEP ISO SC4 UML ISO SC7 Engineering Disciplines 2002-04 - Mike Dickerson, NASA-JPL

  32. Spacecraft Development Using ISO 10303 and Other Standards • Electrical Engineering • Standard: AP210 • Software Mentor Graphics • Status: Prototyped • Rockwell, Boeing • Cabling • Standard: AP212 • Software MentorGraphics • Status: Prototyped • Daimler-Chrysler, ProSTEP • Propulsion • Standard: STEP-PRP • Software:- • Status: In Development • ESA, EADS • Fluid Dynamics • Standard: CFD • Software - • Status: In Development • Boeing, • Software Engineering • Standard::UML - (AP233 interface In Development) • Software:Rational Rose, Argo, All-Together • Status: In Production • Industry-wide • Optics • Standard: NODIF • Software - TBD • Minolta, Olympus • Mechanical Engineering • Standard: AP203, AP214 • Software Pro-E, Cadds, SolidWorks, AutoCad, SDRC IDEAS, Unigraphics, others • Status: In Production • Aerospace Industry Wide, Automotive Industry • Systems Engineering • Standard: AP233 • Software:Statemate, Doors, Matrix-X, Slate, Core, RTM • Status: In development / Prototyped • BAE SYSTEMS, EADS, NASA • Structural Analysis • Standard: AP209 • Software:MSC Patran, Thermal Desktop • Status: In Production • Lockheed Martin, Electric Boat • PDM • Standard: STEP PDM Schema/AP232 • Software:MetaPhase, Windchill, Insync • Status: In Production • Lockheed Martin, EADS, BAE SYSTEMS, Raytheon • Thermal Radiation Analysis • Standard: STEP-TAS • Software:Thermal Desktop, TRASYS • Status: In Production • ESA/ESTEC, NASA/JPL & Langely • Inspection • Standard: AP219 • Software:Technomatics, Brown, eSharp • Status: In Development • NIST, CATIA, Boeing, Chrysler, AIAG • Machining • Standard:: STEP-NC/AP224 • Software::Gibbs, • Status:: In Development / Prototyped • STEP-Tools, Boeing • Life-Cycle Management • Standard: PLCS • Software: SAP • Status: In Development • BAE SYSTEMS, Boeing, Eurostep 2001-12-16 - Jim U’Ren, NASA-JPL File: SLIDE_STEP-in-Spacecraft-Development-Ver4.ppt

  33. STEP AP 210 (ISO 10303-210) Domain: Electronics Design R Interconnect Assembly Printed Circuit Assemblies (PCAs/PWAs) Product Enclosure Die/Chip Packaged Part Printed Circuit Substrate (PCBs/PWBs) Die/Chip Package External Interfaces ~800 standardized concepts (many applicable to other domains) Development investment: O(100 man-years) over ~10 years Adapted from 2002-04 - Tom Thurman, Rockwell-Collins

  34. Rich Features in AP210: PWB tracesAP210 STEP-Book Viewer - www.lksoft.com

  35. Rich Features in AP210: Via/Plated Through Hole Z-dimension details …

  36. Rich Features in AP210: Electrical Component The 3D shape is generated from these “smart features” which have electrical functional knowledge. Thus, the AP210-based model is much richer than a typical 3D MCAD package model. 210 can also support the detailed design of a package itself (its insides, including electrical functions and physical behaviors).

  37. Rich Features in AP210: 3D PCB Assembly

  38. PWA/PWB Assembly Simulation using AP210 User Alerted on Exceptions to Producibility Guidelines Rules (From Definition Facility) Generic Manufacturing Equipment Definitions Specific Manufacturing Equipment Used 2002-03 - Tom Thurman, Rockwell-Collins

  39. AnalogyPhysical Integration Modules  Model Integration Frameworks Wafer Level Packaging RF, Digital, Analog, Optical, MEMS Design System Architecture Stacked Fine-Pitch BGA www.shinko.co.jp System-On-a-Package (SOP) Challenge: Integrating Diverse Technologies www.prc.gatech.edu 2001 ITRS

  40. Recommended Solution Approach • Philosophy: Consider engineering design environmentsas analogous to electronic packaging systems • Leverage international collaboration with other industries • Follow systems engineering approach • Decompose problem into subsystems • Architectures, components (standards, tools, …), and techniques • Identify & define gaps • Identify existing solutions where feasible • Define solution paths • Identify who will “supply”/develop these “components” • Develop & prototype solutions • Advocate solution standardization and vendor support • Test in pilots • Deploy in production usage

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