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NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing. Semiconductor Manufacturing Technology: Semiconductor Manufacturing Processes. Conrad T. Sorenson Praxair, Inc.  1999 Arizona Board of Regents for The University of Arizona. Wafer Preparation.

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Semiconductor manufacturing technology semiconductor manufacturing processes

NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing

Semiconductor Manufacturing Technology: Semiconductor Manufacturing Processes

Conrad T. Sorenson

Praxair, Inc.

 1999 Arizona Board of Regents for The University of Arizona


Semiconductor manufacturing processes

Wafer Benign Semiconductor Manufacturing

Preparation

Design

Front-End

Processes

Thin Films

Photo-

lithography

Ion

Implantation

Etch

Cleaning

Planarization

Test &

Assembly

Semiconductor Manufacturing Processes

  • Design

  • Wafer Preparation

  • Front-end Processes

  • Photolithography

  • Etch

  • Cleaning

  • Thin Films

  • Ion Implantation

  • Planarization

  • Test and Assembly


Design

Wafer Benign Semiconductor Manufacturing

Preparation

Design

Front-End

Processes

Thin Films

Photo-

lithography

Ion

Implantation

Etch

Cleaning

Planarization

Test &

Assembly

Design

  • Establish Design Rules

  • Circuit Element Design

  • Interconnect Routing

  • Device Simulation

  • Pattern Preparation


Pattern preparation

Chrome Pattern Benign Semiconductor Manufacturing

Pellicle

Quartz Substrate

Pattern Preparation

Reticle


Wafer preparation

Wafer Benign Semiconductor Manufacturing

Preparation

Design

Front-End

Processes

Thin Films

Photo-

lithography

Ion

Implantation

Etch

Cleaning

Planarization

Test &

Assembly

Wafer Preparation

  • Polysilicon Refining

  • Crystal Pulling

  • Wafer Slicing & Polishing

  • Epitaxial Silicon Deposition


Polysilicon refining
Polysilicon Refining Benign Semiconductor Manufacturing

Chemical Reactions

Silicon Refining: SiO2 + 2 C  Si + 2 CO

Silicon Purification: Si + 3 HCl  HSiCl3 + H2

Silicon Deposition: HSiCl3 + H2 Si + 3 HCl

Reactants

H2

Silicon Intermediates

H2SiCl2

HSiCl3


Crystal pulling

Quartz Tube Benign Semiconductor Manufacturing

Rotating Chuck

Seed Crystal

Growing Crystal

(boule)

RF or Resistance

Heating Coils

Molten Silicon

(Melt)

Crucible

Crystal Pulling

Process Conditions

Flow Rate: 20 to 50 liters/min

Time: 18 to 24 hours

Temperature: >1,300 degrees C

Pressure: 20 Torr

Materials

Polysilicon Nodules *

Ar *

H2

* High proportion of the total product use


Wafer slicing polishing

silicon wafer Benign Semiconductor Manufacturing

p+ silicon substrate

Wafer Slicing & Polishing

The silicon ingot is sliced into individual wafers, polished, and cleaned.

3/15/98

PRAX01C.PPT Rev. 1.0


Epitaxial silicon deposition

silicon wafer Benign Semiconductor Manufacturing

p- silicon epi layer

p+ silicon substrate

Silicon Sources

SiH4

H2SiCl2

HSiCl3*

SiCl4*

Dopants

AsH3

B2H6

PH3

Etchant

HCl

Carriers

Ar

H2*

N2

Epitaxial Silicon Deposition

Gas

Input

Lamp

Module

Susceptor

Chemical Reactions

Silicon Deposition: HSiCl3 + H2 Si + 3 HCl

Process Conditions

Flow Rates: 5 to 50 liters/min

Temperature: 900 to 1,100 degrees C.

Pressure: 100 Torr to Atmospheric

Quartz

Lamps

Wafers

Exhaust

* High proportion of the total product use


Front end processes

Wafer Benign Semiconductor Manufacturing

Preparation

Design

Front-End

Processes

Thin Films

Photo-

lithography

Ion

Implantation

Etch

Cleaning

Planarization

Test &

Assembly

Front-End Processes

  • Thermal Oxidation

  • Silicon Nitride Deposition

    • Low Pressure Chemical Vapor Deposition (LPCVD)

  • Polysilicon Deposition

    • Low Pressure Chemical Vapor Deposition (LPCVD)

  • Annealing


Front end processes1

Vertical LPCVD Furnace Benign Semiconductor Manufacturing

Exhaust Via

Vacuum Pumps

and Scrubber

Quartz Tube

3 Zone

Temperature

Control

Gas Inlet

Front-End Processes

Chemical Reactions

Thermal Oxidation: Si + O2 SiO2

Nitride Deposition: 3 SiH4 + 4 NH3 Si3N4 + 12 H2

Polysilicon Deposition: SiH4 Si + 2 H2

Process Conditions (Silicon Nitride LPCVD)

Flow Rates: 10 - 300 sccm

Temperature: 600 degrees C.

Pressure: 100 mTorr

Oxidation

Ar

N2

H2O

Cl2

H2

HCl *

O2 *

Dichloroethene *

Polysilicon

H2

N2

SiH4*

AsH3

B2H6

PH3

Nitride

NH3 *

H2SiCl2 *

N2

SiH4 *

SiCl4

Annealing

Ar

He

H2

N2

* High proportion of the total product use


Photolithography

Wafer Benign Semiconductor Manufacturing

Preparation

Design

Front-End

Processes

Thin Films

Photo-

lithography

Ion

Implantation

Etch

Cleaning

Planarization

Test &

Assembly

Photolithography

  • Photoresist Coating Processes

  • Exposure Processes


Photoresist coating processes
Photoresist Coating Processes Benign Semiconductor Manufacturing

photoresist

field oxide

p- epi

p+ substrate

Photoresists

Negative Photoresist *

Positive Photoresist *

Other Ancillary Materials (Liquids)

Edge Bead Removers *

Anti-Reflective Coatings *

Adhesion Promoters/Primers (HMDS) *

Rinsers/Thinners/Corrosion Inhibitors *

Contrast Enhancement Materials *

Developers

TMAH *

Specialty Developers *

Inert Gases

Ar

N2


Exposure processes

photoresist Benign Semiconductor Manufacturing

field oxide

p- epi

p+ substrate

Exposure Processes

Expose

Kr + F2 (gas) *

Inert Gases

N2


Ion implantation

Wafer Benign Semiconductor Manufacturing

Preparation

Design

Front-End

Processes

Thin Films

Photo-

lithography

Ion

Implantation

Etch

Cleaning

Planarization

Test &

Assembly

Ion Implantation

  • Well Implants

  • Channel Implants

  • Source/Drain Implants


Ion implantation1

Focus Benign Semiconductor Manufacturing

Beam trap and

gate plate

Neutral beam and

beam path gated

Neutral beam trap

and beam gate

Y - axis

scanner

X - axis

scanner

Wafer in wafer

process chamber

Equipment Ground

Resolving

Aperture

180 kV

Gases

Ar

AsH3

B11F3*

He

N2

PH3

SiH4

SiF4

GeH4

Solids

Ga

In

Sb

Liquids

Al(CH3)3

Acceleration Tube

90° Analyzing Magnet

Terminal Ground

Ion Source

20 kV

Ion Implantation

junction depth

Process Conditions

Flow Rate: 5 sccm

Pressure: 10-5 Torr

Accelerating Voltage: 5 to 200 keV

* High proportion of the total product use


Wafer Benign Semiconductor Manufacturing

Preparation

Design

Front-End

Processes

Thin Films

Photo-

lithography

Ion

Implantation

Etch

Cleaning

Planarization

Test &

Assembly

Etch

  • Conductor Etch

    • Poly Etch and Silicon Trench Etch

    • Metal Etch

  • Dielectric Etch


Conductor etch

Cluster Tool Benign Semiconductor Manufacturing

Configuration

Etch

Chambers

Wafers

Transfer

Chamber

Loadlock

Gas Inlet

RIE Chamber

Wafer

Transfer

Chamber

Polysilicon Etches

HBr *

C2F6

SF6*

NF3*

O2

Aluminum Etches

BCl3 *

Cl2

Diluents

Ar

He

N2

RF Power

Exhaust

Conductor Etch

Chemical Reactions

Silicon Etch: Si + 4 HBr  SiBr4 + 2 H2

Aluminum Etch: Al + 2 Cl2 AlCl4

Process Conditions

Flow Rates: 100 to 300 sccm

Pressure: 10 to 500 mTorr

RF Power: 50 to 100 Watts

* High proportion of the total product use


Dielectric etch

Contact locations Benign Semiconductor Manufacturing

Cluster Tool

Configuration

Etch

Chambers

Wafers

Transfer

Chamber

Loadlock

Gas Inlet

RIE Chamber

Wafer

Transfer

Chamber

Plasma Dielectric Etches

CHF3*

CF4

C2F6

C3F8

CO *

Diluents

Ar

He

N2

CO2

O2

SF6

SiF4

RF Power

Exhaust

Dielectric Etch

Chemical Reactions

Oxide Etch: SiO2 + C2F6 SiF4 + CO2 + CF4 + 2 CO

Process Conditions

Flow Rates: 10 to 300 sccm

Pressure: 5 to 10 mTorr

RF Power: 100 to 200 Watts

* High proportion of the total product use


Cleaning

Wafer Benign Semiconductor Manufacturing

Preparation

Design

Front-End

Processes

Thin Films

Photo-

lithography

Ion

Implantation

Etch

Cleaning

Planarization

Test &

Assembly

Cleaning

  • Critical Cleaning

  • Photoresist Strips

  • Pre-Deposition Cleans


Critical cleaning

Contact locations Benign Semiconductor Manufacturing

Critical Cleaning

Process Conditions

Temperature: Piranha Strip is 180 degrees C.

RCA Clean

SC1 Clean (H2O + NH4OH + H2O2) *

* SC2 Clean (H2O + HCl + H2O2) *

Piranha Strip

* H2SO4 + H2O2*

Nitride Strip

H3PO4 *

Oxide Strip

HF + H2O *

Dry Strip

N2O

O2

CF4 + O2

O3

Solvent Cleans

NMP

Proprietary Amines (liquid)

Dry Cleans

HF

O2 Plasma

Alcohol + O3


Thin films

Wafer Benign Semiconductor Manufacturing

Preparation

Design

Front-End

Processes

Thin Films

Photo-

lithography

Ion

Implantation

Etch

Cleaning

Planarization

Test &

Assembly

Thin Films

  • Chemical Vapor Deposition (CVD) Dielectric

  • CVD Tungsten

  • Physical Vapor Deposition (PVD)

  • Chamber Cleaning


Chemical vapor deposition cvd dielectric

Metering Benign Semiconductor Manufacturing

Pump

Inert Mixing

Gas

Vaporizer

Direct

Liquid

Injection

Process Gas

LPCVD

Chamber

Gas Inlet

CVD Dielectric

O2

O3

TEOS *

TMP *

Wafer

Transfer

Chamber

RF Power

Exhaust

Chemical Vapor Deposition (CVD) Dielectric

TEOS

Source

Chemical Reactions

Si(OC2H5)4 + 9 O3 SiO2 + 5 CO + 3 CO2 + 10 H2O

Process Conditions (ILD)

Flow Rate: 100 to 300 sccm

Pressure: 50 Torr to Atmospheric

* High proportion of the total product use


Chemical vapor deposition cvd tungsten
Chemical Vapor Deposition (CVD) Tungsten Benign Semiconductor Manufacturing

Input

Cassette

Output

Cassette

Chemical Reactions

WF6 + 3 H2 W + 6 HF

Process Conditions

Flow Rate: 100 to 300 sccm

Pressure: 100 mTorr

Temperature: 400 degrees C.

Wafer

Hander

Wafers

Multistation Sequential

Deposition Chamber

CVD Dielectric

WF6*

Ar

H2

N2

Water-cooled

Showerheads

Resistively

Heated Pedestal

* High proportion of the total product use


Physical vapor deposition pvd

N Benign Semiconductor Manufacturing

S

N

Physical Vapor Deposition (PVD)

Physical

Vapor

Deposition

Chambers

Cluster Tool

Configuration

Wafers

Transfer

Chamber

Loadlock

Process Conditions

Pressure: < 5 mTorr

Temperature: 200 degrees C.

RF Power:

Reactive

Gases

PVD Chamber

Cryo Pump

Barrier Metals

SiH4

Ar

N2

N2

Ti PVD Targets *

Transfer

Chamber

  • e -

+

Wafer

Argon &

Nitrogen

Backside

He Cooling

DC Power

Supply (+)

* High proportion of the total product use


Chamber cleaning

Multistation Sequential Benign Semiconductor Manufacturing

Deposition Chamber

Water-cooled

Showerheads

Resistively

Heated Pedestal

Aluminum

Surface Coating

Process Material Residue

Chamber Cleaning

Chemical Reactions

Oxide Etch: SiO2 + C2F6 SiF4 + CO2 + CF4 + 2 CO

Process Conditions

Flow Rates: 10 to 300 sccm

Pressure: 10 to 100 mTorr

RF Power: 100 to 200 Watts

Chamber Cleaning

C2F6*

NF3

ClF3

Chamber Wall Cross-Section

* High proportion of the total product use


Planarization

Wafer Benign Semiconductor Manufacturing

Preparation

Design

Front-End

Processes

Thin Films

Photo-

lithography

Ion

Implantation

Etch

Cleaning

Planarization

Test &

Assembly

Planarization

  • Oxide Planarization

  • Metal Planarization


Chemical mechanical planarization cmp

Platen Benign Semiconductor Manufacturing

Head

Sweep Slide

Polishing

Head

Load/Unload

Station

Pad

Conditioner

Wafer Handling

Robot & I/O

Carousel

Backing (Carrier) Film

Polyurethane

Pad

Polyurethane

Pad Conditioner

Abrasive

CMP (Oxide)

Silica Slurry

KOH *

NH4OH

H2O

CMP (Metal)

Alumina *

FeNO3

Chemical Mechanical Planarization (CMP)

Process Conditions (Oxide)

Flow: 250 to 1000 ml/min

Particle Size: 100 to 250 nm

Concentration: 10 to 15%, 10.5 to 11.3 pH

Process Conditions (Metal)

Flow: 50 to 100 ml/min

Particle Size: 180 to 280 nm

Concentration: 3 to 7%, 4.1 - 4.4 pH

Wafer

Carrier

Polishing Pad

Slurry

Delivery

*

Wafer

Platen

* High proportion of the total product use.


Test and assembly

Wafer Benign Semiconductor Manufacturing

Preparation

Design

Front-End

Processes

Thin Films

Photo-

lithography

Ion

Implantation

Etch

Cleaning

Planarization

Test &

Assembly

Test and Assembly

  • Electrical Test Probe

  • Die Cut and Assembly

  • Die Attach and Wire Bonding

  • Final Test


Electrical test probe

bonding pad Benign Semiconductor Manufacturing

nitride

Metal 2

p-well

n-well

n-channel transistor

p-channel transistor

p+ substrate

Electrical Test Probe

Defective IC

Individual integrated circuits are tested to distinguish good die from bad ones.


Die cut and assembly
Die Cut and Assembly Benign Semiconductor Manufacturing

Good chips are attached to a lead frame package.


Die attach and wire bonding
Die Attach and Wire Bonding Benign Semiconductor Manufacturing

lead frame

gold wire

bonding pad

connecting pin


Final test
Final Test Benign Semiconductor Manufacturing

Chips are electrically tested under varying environmental conditions.


References
References Benign Semiconductor Manufacturing

1. CMOS Process Flow in Wafer Fab, Semiconductor Manufacturing Technology, DRAFT, Austin Community College, January 2, 1997.

2. Semiconductor Processing with MKS Instruments, Inc.

3. Worthington, Eric. “New CMP architecture addresses key process issues,” Solid State Technology, January 1996.

4. Leskonic, Sharon. “Overview of CMP Processing,” SEMATECH Presentation, 1996.

5. Gwozdz, Peter. “Semiconductor Processing Technology” SEMI, 1997.

6. CVD Tungsten, Novellus Sales Brochure, 7/96.

7. Fullman Company website. “Fullman Company - The Semiconductor Manufacturing Process,” http://www.fullman.com/semiconductors/index.html, 1997.

8. Barrett, Craig R. “From Sand to Silicon: Manufacturing an Integrated Circuit,” Scientific American Special Issue: The Solid State Century, January 22, 1998.


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