1 / 21

Muon Trigger Upgrade LL1 Electronics

Muon Trigger Upgrade LL1 Electronics. Iowa State University John Lajoie Cesar Luiz daSilva Todd Kempel Andy Goers Roy McKay Gary Sleege. RPC1. RPC3. Trigger Algorithm. Momentum selectivity through online sagitta measurement Uses MuTR 1,2,3 and RPC1,3 planes.

kelli
Download Presentation

Muon Trigger Upgrade LL1 Electronics

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Muon Trigger Upgrade LL1 Electronics Iowa State University John Lajoie Cesar Luiz daSilva Todd Kempel Andy Goers Roy McKay Gary Sleege J. Lajoie - Muon Trigger Upgrade Review

  2. RPC1 RPC3 Trigger Algorithm • Momentum selectivity through online sagitta measurement • Uses MuTR 1,2,3 and RPC1,3 planes PHENIX LL1 decision time 40xBCLK (4ms) Implement trigger using fast, parallel logic on FPGA’s J. Lajoie - Muon Trigger Upgrade Review

  3. 12 x xcvr 12 x xcvr 12 x xcvr 12 x xcvr Virtex-5 LX110T Virtex-5 LX110T Virtex-5 LX110T Virtex-5 LX110T Trigger Board Block Diagram One board processes four trigger octants (one octant per tile). (RPC1,3 @ 2.8Gbit) P1 VME Interface P0 (MuTr St2 @ 2.8Gbit) P2 (MuTr St1 @ 2.8Gbit) (MuTr St3 @ 2.8Gbit) Virtex-5 LX110T P3 (7 fibers per octant) J. Lajoie - Muon Trigger Upgrade Review

  4. LL1 Trigger Tile Development • Rev0 Trigger Tile – Nov’07 • Power supply operation and testing • ADuC control, I2C communication • Signal integrity on serial pairs • TDR testing to measure pair impedance • Rev1 Trigger Tile – April’08 • Full population and assembly • Power consumption • FPGA, scaling with GTP use • Testing of FPGA interface • JTAG, PROMS, power-up programming • Serial communication testing • BERT testing on all serial lines • Chain test with MuTr MRG board • Rev2 Trigger Tile – Sept’08 • Minor changes to ease assembly • Revised memory interface and connector More on BERT tests and MRG board tests to follow. J. Lajoie - Muon Trigger Upgrade Review

  5. The LL1 Trigger Tile J. Lajoie - Muon Trigger Upgrade Review

  6. Test Stand Setup • All GTP Connections Verified • Verified with BERR testing • Used Xilinx IBERT tools and GTP internal PRBS generators • All GTP tiles working at 2.8Gbps and 3.125Gbps • Using XpressO +/- 50ppm clock • BERR < 5.1x10-15 with 8b/10b • Tested up to 8 tiles (16 GTP’s) in single LX110T design • Requires heat sink and fan • Current draw as expected (~2A on 3.3V w/all GTP’s) J. Lajoie - Muon Trigger Upgrade Review

  7. MuTr MRG to LL1 Data Format 140MHz Optical driver data[15:0] TLK3101 (TI) 850nm laser FTLF8524E2KNL (finisar) TX_EN to LL1 TX_ER additional idle packet owing to asynchronous system (9.4x14MHz  140MHz) color Carrier Extend (no data) Header next event event data Data format agreed to between LL1 and MuTr FEE group (April ’08 workshop at ISU). idle idle idle ….…… to LL1 14 packets for 1 cycle J. Lajoie - Muon Trigger Upgrade Review

  8. Communication Tests ~30m fiber connecting the two boards LL1 Trigger Tile Two MRG Board Prototypes Laptop for power control, chip monitoring (voltages, temps, etc), Chipscope for signal monitoring Pattern Generator for input J. Lajoie - Muon Trigger Upgrade Review

  9. MRG->LL1 Testing at BNL (Aug ’08) • Optical connection between MRG and LL1 trigger tile established: • Patterns sent from MRG board with alternating parity • Parity calculated and checked at LL1 end • System ran for ~14 hrs w/o error • Clock domain logic in tile FPGA fully tested (REF, 14xBCLK, BMCLK) J. Lajoie - Muon Trigger Upgrade Review

  10. Base Board Design • Base board design and layout nearly complete • Design in final stages at ISU • Many lessons learned from Tile design integrated into base board J. Lajoie - Muon Trigger Upgrade Review

  11. Schedule and Integration • Rev2 Tiles Available Oct 20th • Checkout at ISU to follow • Base Board Schedule • Out for production Oct. 6th • Assembled, in testing Oct. 27th • Algorithm Development/Programming • Underway through Jan. ’09 • Basic trigger functionality at this point • Integration at BNL Dec.’08-March’09 J. Lajoie - Muon Trigger Upgrade Review

  12. BACKUP J. Lajoie - Muon Trigger Upgrade Review

  13. Fiber Data Rates • Data rate on fibers assumes 8b/10b encoding, 16-bit words, two header words (frame header and clock counter) • The data rate on the fiber is then given by: • N is number of data frames Planning on N=12 (nominal ~14xBCLK, or 140Mhz) J. Lajoie - Muon Trigger Upgrade Review

  14. Trigger Tile Stackup (Example): GND 4.0 mils Rogers 4350B 7.7 mils Rev1 (core material, Cu plated on both sides) SGNL4 ~0.7 mils <8.0mil 4450B-DX prepreg 4.3 mil 0.5 oz Cu (Rev1) (two layers of 4 mil, compressed to <8.0mils, trace width adjusted for controlled impedance) VLINRA http://www.rogers-corp.com J. Lajoie - Muon Trigger Upgrade Review

  15. Logic Estimate • Assume the logic required scales like the number of input bits, scale MuID LL1 logic required: • 1920 bits for MuID LL1, processed in five XCV2000E chips • 38,400 logic cells • At best 21% utilization • 1248 bits for MuTr+RPC LL1, to be processed in one chip • Assume we can go to 50% occupancy • Require 38,400*5*(1248/1920)*(21/50) = 52,416 logic cells • Possible Xilinx Options: • Virtex-5: • XC5VLX85T (12 Rocket I/O, 82,944 logic cells) • XC5VLX110T (16 Rocket I/O, 110,592 logic cells) J. Lajoie - Muon Trigger Upgrade Review

  16. MuTr LL1 Channel Count Channel Counts: Fibers will come off the detector at 1.25Gbit (96 bits) and combined to 2.8 Gbit fibers (192 bits). Fiber Counts (@ ~2.8Gbit) : NOTE: MuTr clustering to be done at FEM level. J. Lajoie - Muon Trigger Upgrade Review

  17. RPC LL1 Channel Count RPC channel counts assume channels OR’d in pairs of rings at FEM level, highest channel count in pair used. Channel Counts: Assume RPC1a and RPC1b OR performed at FEM level: Fiber Counts (@ ~2.8Gbit) : J. Lajoie - Muon Trigger Upgrade Review

  18. Virtex-5 GTP Tile Layout: • Each tile has two transmitter/receiver pairs with shared clock logic • Loopback capabilities in each TX/RX pair • Integrated 8b/10b encoding • Integrated comma detection and bitstream alignment J. Lajoie - Muon Trigger Upgrade Review

  19. Virtex-5 GTP Tile Layout (II): 36-bit dual ported BRAM (32 bits data, 4 bit CHARISK) B U F F E R All of this functionality is configurable via the RocketIO Wizard and HDL wrappers, ending in connection through dual-ported RAM J. Lajoie - Muon Trigger Upgrade Review

  20. Tile Rev2 Changes • LED installed backwards • Update silk on tile, notify assembler • Changed P/S enable pulldowns to 10k • Component change • Silk Labels incorrect on Test Board • DOUT[9] +/- labels reversed • Termination incorrect on DDR-2 Socket • We don’t plan to use this for our application • Rev2 will use different DDR memory connector/layout • Changes to SwIOV to allow 3.3V/1.8V external signals • Move some resistors/caps around BGA components • Allow easier replacement if necessary • Adjust some components/footprints • Battery clip leads • Some components have short leads for this thick of a board • Added clip-on fan+heatsink • Will add fan header and RPM readback in Rev2 • ROHS Compliant parts and board J. Lajoie - Muon Trigger Upgrade Review

  21. Power Supply Issues • Experienced high failure rate of TPS74401 Linear Regulators • Three failed (on three different boards) within first two weeks of operation • Parts removed from board and replaced • Nice to know we can do this • Sent to TI for full failure analysis • Decapsulated two failed units • Conclusion: ESD on input • Traced to test stand at NMI • Power supply grounds floating • Don’t believe this is a critical component or design flaw. J. Lajoie - Muon Trigger Upgrade Review

More Related