Set associative cache
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Set-Associative Cache. Chapter 7. Cache Configuration. The set of blocks in a cache can be configured as: Direct mapped N-way set associative Fully-associative Associative cache have shown to result in lowering miss rate.

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Set-Associative Cache

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Set associative cache

Set-Associative Cache

Chapter 7


Cache configuration

Cache Configuration

  • The set of blocks in a cache can be configured as:

    • Direct mapped

    • N-way set associative

    • Fully-associative

  • Associative cache have shown to result in lowering miss rate.

  • As N increases, the number of index bits decreases and it reaches 0 for a fully-associative cache.

  • Lets look at a 4-way set associative cache fig.7.17


Cache configuration1

Cache configuration

  • Direct map: one main memory has only one possible cache block map (direct map).

  • N-way set associative cache has N block choices per main memory block.

  • For example, 2-way set-associative has two possible choices for every main memory block.

  • See Fig.7.14

  • The comparator complexity increases with N.


Performance with cache p 505 506

Performance with cache (p.505-506)

  • Processor with base CPI of 1, assuming 100% hit ratio in primary cache, and clock rate of 5Ghz.

  • Assume main memory access time of 100ns including all the miss handling.

  • Miss rate per instruction at primary cache 2%.

  • How mush faster will the processor be if we add a another level of cache with following characteristics?

    • Secondary cache has 5ns for hit or miss, and can reduce miss ratio to main memory to 0.5%.


Solution performance measured in cpi

Solution: Performance measured in CPI

  • With only primary cache:

    • 1 + (2/100) X (5Ghz*100ns) = 11 CPI

  • With secondary cache:

    • No miss: 1 +

    • L1 miss : (2/100) X (5Ghz *5ns) +

    • L2 miss: (0.5/100) X (5Ghz * 100ns) =

    • 1 + 0.5 + 2.5 = 4 CPI


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