Fetch1

1. Fetch1 Fetch2 Fetch3 Decode AND ADD NOT JMP RET JSR BR LD ST LC3 Controller State Machine

2. Fetch1 Fetch2 Fetch3 Decode LC3 Controller State Machine AND ADD NOT JMP RET JSR BR LD ST

3. Fetch1 Fetch2 Fetch3 Decode LC3 Controller State Machine AND ADD NOT JMP RET JSR BR LD ST

4. Fetch1 Fetch2 Fetch3 Decode LC3 Controller State Machine All other instructions AND ADD NOT JMP RET JSR BR LD ST

5. Verilog State Machine State Registers Next State logic Output forming Logic

6. Next State Logic Fetch 0 Fetch 1 Fetch 2 Decode Decode JMP assign NS[1] = CS[0] assign NS[5] = CS[4] & (opcode = 0001 +…

7. Output Forming Logic enaPC = CS[0] + CS[7] + CS[10] enaALU = CS[5] & IR[15:12]==4’b0101

8. Verilog State Machine • Two block state machine • One n-bit register where n is the number of states • This clocks next_state through to current_state • Combinational logic block • This determines value of next_state and control signals

9. Use parameters parameter Fetch0 = 10’b000000001; parameter Fetch1 = 10’b000000010; parameter Fetch2 = 10’b000000100; . . .

10. Combinational Logic Block always @(current_state) begin (refer to inactive.tcl reset values) case(current_state) Fetch0: begin (refer to TCL file for fetch0); next_state <= Fetch1; end Fetch1: begin (refer to TCL file for fetch1); next_state <= …; end . . . (SomeInstruction): begin if IR[6] = 1’b1: (somesignal) <= 1’b1; else (somesignal) <= 1’b0; end endcase end