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Graph-IC Verification

Graph-IC Verification. by. Hello!. Why are we here? Report of our experience in verifying a complex and highly configurable IP. Our problems might be yours. Graph-IC. DUT Overview. Display engine: Fetch data Process pixels Output video formating Multi channel / overlays.

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Graph-IC Verification

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  1. Graph-IC Verification by

  2. Hello! • Why are we here? • Report of our experience in verifying a complex and highly configurable IP Our problems might be yours Gregory Faux (STMicroelectronics), Dennis Ramaekers (ST-Ericsson)

  3. Graph-IC Gregory Faux (STMicroelectronics), Dennis Ramaekers (ST-Ericsson)

  4. DUT Overview • Display engine: • Fetch data • Process pixels • Output video formating • Multi channel / overlays Gregory Faux (STMicroelectronics), Dennis Ramaekers (ST-Ericsson)

  5. Where Complexity Explodes… • Each stage presents high configurability • High flexibility achieved by decoupling each stage Memory Memory Buffer Buffer Buffer Buffer PP1 PP1 PP2 PP2 PP n PP n • Legal configurations are hard to generate, with complex resources management • … recurrent problem raised @each verification level Buffer Buffer Gregory Faux (STMicroelectronics), Dennis Ramaekers (ST-Ericsson)

  6. CRV LIMITATIONS Gregory Faux (STMicroelectronics), Dennis Ramaekers (ST-Ericsson)

  7. Original Approach Constraint Random Verification (VIPs, scbd, sequences…) C reference model Test Bench Virtual sequences Scoreboard Model VIP VIP DUV if0 if1 Gregory Faux (STMicroelectronics), Dennis Ramaekers (ST-Ericsson)

  8. Constraints Based Modeling • Multiple stages, each requiring a large constraints set • Additional constraints required to ensure valid data path • Data paths can be multiple and re-configurable Flexible data path High configurability Resource Management Tedious generation of legal configurations ! Gregory Faux (STMicroelectronics), Dennis Ramaekers (ST-Ericsson)

  9. Challenges • Coverage closure • Constraints set was hard to develop and maintain • Huge test suite • Some scenario still missing • Horizontal reuse • Important constraint subset tightly linked to IP version • Vertical reuse • Different verification approaches and languages Gregory Faux (STMicroelectronics), Dennis Ramaekers (ST-Ericsson)

  10. Graph Based Verification Main Concepts Gregory Faux (STMicroelectronics), Dennis Ramaekers (ST-Ericsson)

  11. Overview • User describes sequential steps required to generate verification scenario using graph • Nodes can be used to perform • Configuration generation • TB interaction: data injection/grabbing, synchronization on events • File generation Three Types of Goals Sequence Goal – evaluate ALL children Select Goal – evaluate ONE child Leaf Goal – has NO child Gregory Faux (STMicroelectronics), Dennis Ramaekers (ST-Ericsson)

  12. Graph Evaluation • Ordered graph walk • Multiple and concurrent evaluations are possible • Executing a node means evaluating the corresponding C++ function goal sequence0 {…} goal sequence1 {…} goal leaf2 {…} goal select1 {…} goal leaf3 {…} goal leaf1 {…} Gregory Faux (STMicroelectronics), Dennis Ramaekers (ST-Ericsson)

  13. new Graph Evaluation (cont’d) • Constraints can be applied to any select child • If masked, a child will never be selected • If forced, a child will always be selected • Constraints can be static and/or dynamic • Goal may be redefined (body and subgraph) Gregory Faux (STMicroelectronics), Dennis Ramaekers (ST-Ericsson)

  14. Application Gregory Faux (STMicroelectronics), Dennis Ramaekers (ST-Ericsson)

  15. Application On Our ControllerIP Testbench Scenario Driver Test Bench Virtual sequences Scoreboard Model VIP VIP DUV if0 if1 Gregory Faux (STMicroelectronics), Dennis Ramaekers (ST-Ericsson)

  16. Application On Our ControllerSystem Test Generation C program Scenario Driver Test Bench CPU Infra IP Infra IP Mem Interconnect System VIP VIP M2M IP I/O IP I/O IP Gregory Faux (STMicroelectronics), Dennis Ramaekers (ST-Ericsson)

  17. Graph Overview Gregory Faux (STMicroelectronics), Dennis Ramaekers (ST-Ericsson)

  18. Benefits Gregory Faux (STMicroelectronics), Dennis Ramaekers (ST-Ericsson)

  19. Coverage Closure • The sequential nature of graph evaluation permitted • An easy decomposition of the original problem • An easy datapath modeling • Smooth resources management • Generation of unexplored scenario • New bugs found • Re-writing of the test suite • From basic to very complex tests • Faster Verification closure Gregory Faux (STMicroelectronics), Dennis Ramaekers (ST-Ericsson)

  20. Project specific Common new Horizontal reuse Maintenance and IP derivatives • Easy derivatives support via several select and leaf goals redefinitions • Project independent common pool of files for easy maintenance • Few configuration specific files are needed per IP version • Time to first valid test divided by 2 20 of 22 Gregory Faux (STMicroelectronics), Dennis Ramaekers (ST-Ericsson)

  21. Drive VIP Write C C program Vertical Reuse From IP to SoC • Most of the graph model is common to both platforms • Natural split between nodes that are platform agnostic and those which are not VIP Gregory Faux (STMicroelectronics), Dennis Ramaekers (ST-Ericsson)

  22. Conclusion CRV faces some limits on really complex IPs Our experience with Graph Based Verification was positive Productivity and quality improved We applied it @IP and @SoC Vertical reuse enabler System tests (deployment on-going) Gregory Faux (STMicroelectronics), Dennis Ramaekers (ST-Ericsson)

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