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Chapter 20 Smaller Tables. Chien -Chung Shen CIS, UD [email protected] Problem. Big page table 32-bit address space (2 32 bytes) with 4KB (2 12 byte) pages and 4-byte page table entry 2 32 /2 12 pages and 4MB page table per process Problem: how to make page table smaller?

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Presentation Transcript
problem
Problem
  • Big page table
  • 32-bit address space (232 bytes) with 4KB (212 byte) pages and 4-byte page table entry
  • 232/212 pages and 4MB page table per process
  • Problem: how to make page table smaller?
  • The simplest way
    • bigger pages
    • e.g., 16KB pages -> 1MB page table
    • internal fragmentation
hybrid approach
Hybrid Approach
  • Paging + segmentation

PFN validprotpresentdirty

10 1 r-x 1 0

- 0 — - -

- 0 — - -

- 0 — - -

23 1 rw- 1 1

- 0 — - -

- 0 — - -

- 0 — - -

- 0 — - -

- 0 — - -

- 0 — - -

- 0 — - -

- 0 — - -

- 0 — - -

28 1 rw- 1 1

4 1 rw- 1 1

  • Anythingbad?
    • toomanyinvalidPTEs
paging segmentation
Paging + Segmentation
  • One page table per segment
    • base (physical address of page table) + bounds
    • 3 page tables for code, heap, and stack
    • on TLB miss, use Segto decide which base/bounds

SN = (VirtualAddress & SEG_MASK) >> SN_SHIFT // Seg

VPN = (VirtualAddress & VPN_MASK) >> VPN_SHIFT

AddressOfPTE= Base[SN] + (VPN * sizeof(PTE))

  • Issues:
    • segmentation is not quite flexible (e.g., sparsely-used heap)
    • external fragmentation caused by page tables
multi level page tables
Multi-level Page Tables
  • How to get rid of those invalid regions in page table (instead of keeping them in memory) ?
    • turns linearpage table into something like a tree
    • chop up page table into page-sized units
    • if an entire page of PTEs is invalid, don’t allocate that page of page table at all
    • page directory

PFN validprotpresentdirty

10 1 r-x 1 0

- 0 — - -

- 0 — - -

- 0 — - -

23 1 rw- 1 1

- 0 — - -

- 0 — - -

- 0 — - -

- 0 — - -

- 0 — - -

- 0 — - -

- 0 — - -

- 0 — - -

- 0 — - -

28 1 rw- 1 1

4 1 rw- 1 1

multi level page tables1
Multi-level Page Tables

Page directory entry (PDE)

multi level p age tables
Multi-level Page Tables
  • Pros
    • page-table space allocated is proportional to amount of address space used
    • growing page table by getting more page frames (which could be anywhere in physical memory
  • Cons
    • on TLB miss, need two memory accesses to get translation info (one for page directory and one for PTE itself)
      • time-space trade-off
    • complexity: perfection is finally attained not when there is no longer anything to add, but when there is no longer anything to take away-- Antoine de Saint-Exupery
inverted page table
Inverted Page Table
  • Instead of having many page tables (one per process), a single page table that has an entry for each physical page of the system
    • which process is using this page (frame)
    • which virtual page of that process maps to this physical page
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