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Semiconductor Modeling And Test Chip Design for Characterization of Radiation Effects. Sotiris Athanasiou National Trainee, TEC-EDM Supervisors: Boris Glass, Richard Jansen. SCOPE. Radiation Effects Semiconductor Modeling TCAD modeling and Doping problem

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slide1

Semiconductor Modeling And Test Chip Design for Characterization of Radiation Effects

Sotiris Athanasiou

National Trainee, TEC-EDM

Supervisors:

Boris Glass, Richard Jansen

slide2

SCOPE

Radiation Effects

Semiconductor Modeling

  • TCAD modeling and Doping problem
  • Compact Models and extensions on verilogA

Test Chip

  • Muxes
  • Test Structures
  • WideBand Amplifier
  • Layout

Rad Effects on SRAM FPGA designs| Sotiris Athanasiou | ESTEC,NL| Data doc | Presentation| Pag. 2

slide3

Radiation Effects

Space is a difficult place for electronics to operate!

Ionized Particles and protons hit the device:

TID

SEE

SEU,MBU,SEFI,SEL,SEB,SEGR,SET

Space engineering,

Techniques for Radiation Effects Mitigation in ASICs and FPGAs

European Space Agency

Space engineering,

Calculation of radiation and its effects and margin policy handbook

European Space Agency

Rad Effects on SRAM FPGA designs| Sotiris Athanasiou | ESTEC,NL| Data doc | Presentation| Pag. 3

slide4

Total Ionizing Dose

TID creates trapped charge in the MOS structure in MOSFET:

  • Vth Shift
  • TID leakage currents
slide5

Single Event Transient

More complex phenomena:

a)A plasma track with e-h pairs is created

b)A path of free carriers between p and n areas – funnel

c)Charge generated outside diffuses to junction

slide6

Why this work

Usually testing is done afterwards more on gate level, and less on transistor level.

Radiation effects not available in simulation of space electronics.

Same concept at ESD design

  • Requires Technology information for simulation
slide7

TCAD model towards electrical behavior under radiation 1/3

TCAD commercial software extended with Geant4 (high energy physics simulator)

Technology

parameters

Electrical behavior under radiation

3d Mesh

Geant4 simulations

GDSII

slide8

TCAD model towards electrical behavior under radiation 2/3

Correctness of Technology parameters:

Technology

parameters

/home/soathana/Desktop/TCAD/IdVd.png

/home/soathana/Desktop/TCAD/IdVd.png

/home/soathana/Desktop/TCAD/IdVd.png

/home/soathana/Desktop/TCAD/IdVd.png

TCAD model

Drift diffusion simulation

Spice simulation

Foundry spice model

results

slide9

TCAD model towards electrical behavior under radiation 3/3

TCAD modeling:

Technology parameters extracted from DESMICREX study

And foundry PDK info

a)Major problem remains Doping profiles 1D vs 3D

Without foundry access it is difficult to obtain Doping.

Methods exist to extract from electrical behavior doping, with some accuracy rely on development of custom code.

b)Luck of methodology on parameters to match

slide10

Compact Models 1/4

Compact Model approach to overcome these issues

Umc 90 nm PDK BSIM4 Compact Model

Use of Silvaco VerilogA BSIM4 implementation

  • Model card extraction into VerilogA model
  • Fix errors/ remove unused code
  • Implement SET, TID leakage into modified model
  • simulate
slide11

Compact Models 2/4

VerilogA electrical behavior against cadence implementation.

Tested against dedicated Matlab model.

A lot of interesting issues arise regarding to what

extent parameters need to be matched IV, CV,

Vth, Idiode e.t.c.

Compact Model Approach offers a lot of

advantages:

1)Access to equation parameters as well as device parameters

2)Better behavior with respect to paracitics

3)No circuit modifications

4)Foundry sensitive parameters not required

slide12

Compact Models 3/4

compact model SET simulation compact model TID leakage simulation

slide13

Compact Models 4/4

  • Parameters extracted from relevant available publications
  • This does gives an indication but not specific values.
  • Data can lead to predictions but in some cases can lead to over/under estimating the behavior
  • Need experimental results to fine tune the equations (parameter extraction)
slide14

Characterization Test Chip and compact model modification

Umc180 example, substrate resistor network.

rbodyMod = 0 (Off)

rbodyMod = 1 (On)

rbodyMod = 2 (On : Scalable Substrate Network): {5R/3R/1R}

Does rbodyMod 0 means no res?

NO!

slide15

Characterization Test Chip Design

Must have a large number of devices to characterize

Minimum number of pins possible

Must facilitate a large number of measurements

MUX architecture

slide16

Characterization Test Chip Design

1K devices of each type, placed in 5 rows of 200

  • Investigate charge sharing

Possible types of measurements

  • CV
  • IV
  • Noise
  • Matching
  • TID leakage
  • SET pulse
  • 4 terminal (Kelvin) measurements
slide17

Characterization Test Chip Design

Wide Band Amplifier to test behavior under high frequencies.

Extract SET pulse shape for first time.

slide18

Characterization Test Chip Design

Building test benches to test functionality

A.D. OP27 behavioral model for simulation purposes

slide19

Characterization Test Chip layout

Test Structures

-generated automatically through cadence SKILL

-Each block contains 14K DUTs

slide21

Future Work

Finalize Test Chip->Tape out

Measurements

Fitting Measurement data to Models-> extract parameters

Insert parameters back to models

Once proof of concept verified, can easily generate new test structures and fabricate next characterization chips.

Rad Effects on SRAM FPGA designs| Sotiris Athanasiou | ESTEC,NL| Data doc | Presentation| Pag. 21

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