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FEI4 CLKGEN. Andre Kruth FE-I4 CLKGEN Jan. 25 th 2010. Test Bench. CLKGEN TOP. Layout FEI4 CLKGEN. SimRes nom PEX C+CC. 80MHz single-ended CLK. 320MHz single-ended CLK. VSS current. SimRes nom PEX C+CC. Acquiring 320MHz. Acquiring 80MHz. SimRes slow PEX C+CC. 80MHz single-ended.

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Fei4 clkgen

FEI4 CLKGEN

Andre Kruth

FE-I4 CLKGEN

Jan. 25th 2010





Simres nom pex c cc
SimRes nom PEX C+CC

80MHz single-ended CLK

320MHz single-ended CLK

VSS current


Simres nom pex c cc1
SimRes nom PEX C+CC

Acquiring 320MHz

Acquiring 80MHz


Simres slow pex c cc
SimRes slow PEX C+CC

80MHz

single-ended

80MHz

320MHz

320MHz

single-ended

VSS current


Simres fast pex c cc
SimRes fast PEX C+CC

80MHz

single-ended

80MHz

320MHz

320MHz

single-ended

VSS current



Additionally
Additionally

… I checked that Adber‘s biasing gives me the biasing currents I need.




Type ii pfd cp pll
Type II PFD-CP PLL

fref=40MHz

fout=40/80/160/320MHz

Simple loss of lock detection

X

only on

demonstrator



Loss of lock detection @ set
Loss of Lock Detection @ SET

Settling of Vctrl

Settling of Vctrl

Settling of Vctrl

Settling of Vctrl

  • Settling time < 1.5  μs (all corners) from extracted simulation

  • Nominal settling time to 2 % envelope t=653 ns

  • Settling time < 1.5  μs (all corners) from extracted simulation

  • Nominal settling time to 2 % envelope t=653 ns

  • Settling time < 1.5  μs (all corners) from extracted simulation

  • Nominal settling time to 2 % envelope t=653 ns

  • Settling time < 1.5  μs (all corners) from extracted simulation

  • Nominal settling time to 2 % envelope t=653 ns


Measurement Data

Measurement Data

>5.6

>5.6

>5.6

ns

ns

ns

mV

mV

mV

>5.6

>5.6

ns

ns

mV

mV

284

284

284

284

284

T= 6.25ns

T= 6.25ns

T= 6.25ns

-

-

Eye diagram of 160

MBit/s serialized data stream

MBit/s serialized data stream

using 80

using 80

MHz PLL clock output with on

MHz PLL clock output with on

-

-

chip digital

chip digital

test logic

test logic

  • Measurement Data

  • Eye diagram of 160 MBit/s serialized data stream using 80 MHz PLL clock output with on-chip digital test logic

  • Clock jitter and duty cycle measurements

  • Measurement Data

  • Eye diagram of 160 MBit/s serialized data stream using 80 MHz PLL clock output with on-chip digital test logic

  • Clock jitter and duty cycle measurements

T= 6.25ns

T= 6.25ns

>5.6 ns

>5.6 ns

284 mV

284 mV

Pulser 81134A time jitter rms 2 ps, Scope TDS5104B 5 GS/s, 1 GHz

*Measurement setup and equipment limit accurarcy

Pulser 81134A time jitter rms 2 ps, Scope TDS5104B 5 GS/s, 1 GHz

*Measurement setup and equipment limit accurarcy


Measurements on demonstrator
Measurements on Demonstrator

Pulser 81134A time jitter rms 2 ps, Scope TDS5104B 5 GS/s, 1 GHz

*Measurement setup and equipment limit accurarcy










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