FEI4 CLKGEN

1. FEI4 CLKGEN Andre Kruth FE-I4 CLKGEN Jan. 25th 2010

2. Test Bench

3. CLKGEN TOP

4. Layout FEI4 CLKGEN

5. SimRes nom PEX C+CC 80MHz single-ended CLK 320MHz single-ended CLK VSS current

6. SimRes nom PEX C+CC Acquiring 320MHz Acquiring 80MHz

7. SimRes slow PEX C+CC 80MHz single-ended 80MHz 320MHz 320MHz single-ended VSS current

8. SimRes fast PEX C+CC 80MHz single-ended 80MHz 320MHz 320MHz single-ended VSS current

9. Locking to 25ns +/- 0.5ns Reference CLK 80MHz mean 320MHz mean

10. Additionally … I checked that Adber‘s biasing gives me the biasing currents I need.

11. Thanks for your attention!

12. BACKUP

14. Type II PFD-CP PLL fref=40MHz fout=40/80/160/320MHz Simple loss of lock detection X only on demonstrator

15. Vctrl Settling

16. Loss of Lock Detection @ SET Settling of Vctrl Settling of Vctrl Settling of Vctrl Settling of Vctrl • Settling time < 1.5  μs (all corners) from extracted simulation • Nominal settling time to 2 % envelope t=653 ns • Settling time < 1.5  μs (all corners) from extracted simulation • Nominal settling time to 2 % envelope t=653 ns • Settling time < 1.5  μs (all corners) from extracted simulation • Nominal settling time to 2 % envelope t=653 ns • Settling time < 1.5  μs (all corners) from extracted simulation • Nominal settling time to 2 % envelope t=653 ns

17. Measurement Data Measurement Data >5.6 >5.6 >5.6 ns ns ns mV mV mV >5.6 >5.6 ns ns mV mV 284 284 284 284 284 T= 6.25ns T= 6.25ns T= 6.25ns - - Eye diagram of 160 MBit/s serialized data stream MBit/s serialized data stream using 80 using 80 MHz PLL clock output with on MHz PLL clock output with on - - chip digital chip digital test logic test logic • Measurement Data • Eye diagram of 160 MBit/s serialized data stream using 80 MHz PLL clock output with on-chip digital test logic • Clock jitter and duty cycle measurements • Measurement Data • Eye diagram of 160 MBit/s serialized data stream using 80 MHz PLL clock output with on-chip digital test logic • Clock jitter and duty cycle measurements T= 6.25ns T= 6.25ns >5.6 ns >5.6 ns 284 mV 284 mV Pulser 81134A time jitter rms 2 ps, Scope TDS5104B 5 GS/s, 1 GHz *Measurement setup and equipment limit accurarcy Pulser 81134A time jitter rms 2 ps, Scope TDS5104B 5 GS/s, 1 GHz *Measurement setup and equipment limit accurarcy

18. Measurements on Demonstrator Pulser 81134A time jitter rms 2 ps, Scope TDS5104B 5 GS/s, 1 GHz *Measurement setup and equipment limit accurarcy

19. PLL TOP

20. PFD

21. CP

22. VCO

23. DIV16

24. DIV2

25. CONV_BUF

26. MUX