Gate Sizing for Cell Library Based Designs

1. Gate Sizing for Cell Library Based Designs Shiyan Hu*, Mahesh Ketkar**, Jiang Hu* *Dept of ECE, Texas A&M University **Intel Corporation

2. Outline • Introduction • Motivation • Problem Formulation • Algorithms • Continuous solution guided dynamic programming • Node pruning and Stage pruning • Locality Sensitive Hashing based pruning • Experimental Results • Conclusion

3. Gate Sizing Problem Gate sizing for timing-power tradeoff • Size a gate • Gate power • Driving resistance • Input capacitance • Gate sizing problem • Minimize power subject to timing constraint

4. Continuous Gate Sizing X1 Continuous problem formulation Minimize Area (Power) Subject to: Delay  T Xmin X  Xmax 1 X3 3 2 X2 • Previous works • Fishburn and Dunlop, ICCAD’85 • Sapatnekar, Rao, Vaidya, and Kang TCAD ’93 • Chen, Chu, and Wong, TCAD’99

5. Motivation • Trend: cell library based design • Discrete gate sizes • Need to round continuous gate sizes • Sparseness of gate library  big rounding error Timing violation

6. Nearest Rounding Does Not Work • Continuous solution by mathematical programming • Rounding continuous sizes to nearest discrete sizes

7. Discrete Gate Sizing • Very few existing approach • GS approach [Coudert, TVLSI’97] • Trial-and-error style algorithm • Based on slacks, pick a group of gates for sizing • Random perturbation • Repeat until convergence • Significant room for improvement

8. Our Choices • Discrete gate sizing is an integerprogramming problem • Hard to solve for large circuits • Rounding? • Not good solution quality • Very fast • Dynamic programming? • Best solution quality • Computationally prohibitive

9. Our Idea • Dynamic programming based rounding • Continuous solution guided dynamic programming • Largely reduce search space • Keep solution quality • At each cell, try discrete gate sizes around the obtained continuous size • For “critical” cells, try more gate sizes

10. For each gate, sizing around continuous solution and perform node pruning Stage pruning Locality sensitive hashing based pruning Overall Flow Circuit partitioning Process stage by stage Pick best solutions at PO

11. Circuit Partitioning A cutline A stage - solution propagation A cutline – prune solutions for acceleration

12. Dynamic Programming Based Rounding Try gate sizes around continuous solution For timing critical nodes, try more sizes

13. Pruning For Acceleration • Three types of pruning • Node pruning • Inside a stage • Stage pruning • At cutline • Locality Sensitive Hashing based pruning • At cutline

14. Node Pruning (I) • Solution Characterization • A solution s is characterized by D(s) and W(s). • D(s): maximum delay from any primary input to any processed gate • W(s): cumulative gate area for all processed gates • Node Pruning • Two solutions s1, s2 • s1 is pruned if • D(s1)  D(s2): larger delay, and • W(s1)  W(s2): larger area.

15. D D Node Pruning (II) Pruned 2x 1x Solution 1: (D,W)=(11,4) 1x 1x 1x Solution 2: (D,W)=(10,3) 1x

16. Stage Pruning • Solution Characterization • A solution s is characterized by f(s) and W(s). • f(s) measures the proximity to the continuous solution • gatei: discrete size, gateic: continuous size • W(s): cumulative gate area for all processed gates • Stage Pruning • Two solutions s1, s2 • s1 is pruned if • f(s1)  f(s2): farther to continuous solution, and • W(s1)  W(s2): larger area.

17. Locality Sensitive Hashing Based Pruning • Maintain diversity in solutions • Do not spend timein checkingsimilar solutions • How? • Cluster solutions • For each cluster, pick a few representative solutions for propagation

18. Solution Clustering • A gate  a dimension • Coordinate = gate implementation ID • Large circuit  many dimensions • Efficient clustering needed • Most existing approaches does not scalewell with dimensionality

19. Locality Sensitive Hashing • For m solutions in d dimensions,clustering runs in only O(dmlogm) time • Linear in dimension • Idea: • For a solution, concatenate coordinates inall d dimensions to a single string • Map it to a much shorter one while preserving distance properties • Many solutions  many short strings. Cluster them.

20. Concatenate discrete gate sizes to form a string 1, 2, 5 00001,00011,11111 Unary representation Solution 1 5x 2x 1x

21. Concatenate discrete gate sizes to form a string 1, 2, 3 00001,00011,00111 Unary representation Solution 2 2x 3x 1x

22. 01011 Solution 1 01001 Solution 2 Hashing (I) Randomly pick k=5 locations 00001,00011,11111 Solution 1 00001,00011,00111 Solution 2 Shorter strings

23. Hashing (II) • Same shorter strings  Hash to same bucket • Indyk et al, prove that • With large probability, geometrically close points are hashed together and geometrically far-apart points are hashes into different buckets. • A bucket = a cluster.

24. Experimental Setup • ISCAS’85 benchmark circuits • X86 computer with 3.2Ghz CPU and 1G memory • 130nm technology • 10 geometrically spaced gate sizes per gate type • Compare to nearest rounding and GS approach

25. Comparison on Slack and Area Slack for GS: 2ps - 21ps Slack for ours: 1ps - 45ps Area saving ratio over GS Slack from rounding: Slack(ps) Area Reduction

26. CPU Comparison

27. Observations • Nearest rounding introduces significanttiming violations • Our algorithm saves 9%-31% area over GS while still improving slacks in many cases • Runtime of our algorithm is on average 1.7x of GS.

28. Delay-Cost Tradeoff • Provide more choices to designers • Help users get better timing constraint for circuit • Two continuous solutions to guide our approach and two curves are obtained

29. Conclusion • Propose a dynamic programming algorithm for discrete gate sizing problem. • Reduce search space by continuous solution guider. • Node pruning, Stage pruning, and Locality Sensitive Hashing based pruning for improving runtime. • 9%-31% area reduction compared to GS. • Future work seeks to handling variations inour approach.