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CMPE 325 Computer Architecture II

CMPE 325 Computer Architecture II. Cem Erg ün Eastern Med iterranean University. Assembly Language Basics. Evolution of Multilevel Machines. Bare hardware Microprogramming Operating system Compilers Hardware / software interface Simple ISA CISC RISC FISC. Computer Organization.

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CMPE 325 Computer Architecture II

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  1. CMPE 325 Computer Architecture II Cem Ergün Eastern Mediterranean University Assembly Language Basics

  2. Evolution of Multilevel Machines • Bare hardware • Microprogramming • Operating system • Compilers • Hardware / software interface • Simple ISA • CISC • RISC • FISC CMPE 325Ch. #3

  3. Computer Organization Von Neumann Machine CMPE 325Ch. #3

  4. Classifying ISAs • Accumulator (before 1960): • 1 address add A acc <- acc + mem[A] • Stack (1960s to 1970s): • 0 address add tos <- tos + next • Memory-Memory (1970s to 1980s): • 2 address add A, B mem[A] <- mem[A] + mem[B] • 3 address add A, B, C mem[A] <- mem[B] + mem[C] • Register-Memory (1970s to present): • 2 address add R1, A R1 <- R1 + mem[A] • load R1, A R1 <_ mem[A] • Register-Register (Load/Store) (1960s to present): • 3 address add R1, R2, R3 R1 <- R2 + R3 • load R1, R2 R1 <- mem[R2] • store R1, R2 mem[R1] <- R2 CMPE 325Ch. #3

  5. Classifying ISAs CMPE 325Ch. #3

  6. Design Principles • CISC vs. RISC • Instructions directly executed by hardware • Maximize instruction issue rate (ILP) • Simple instructions (easy to decode) • Access to memory only via load/store • Plenty of registers • Pipelining CMPE 325Ch. #3

  7. Instruction set vs. Hardware • The instruction set of a computer is • the atomic elements of the program, • directly related to the hardware • For a better processor design, • the instructions shall be “simple”, and • their execution shall be fast. • Properties of the MIPS instruction set • instructions optimized for C and Pascal. • implementation in hardware is simple. CMPE 325Ch. #3

  8. Design Principles of RISC Processor • Four Underlying Design Principles: • Simplicity Favors Similarity • Smaller is faster • Good design demands compromise • Make the common case faster CMPE 325Ch. #3

  9. Programming Languages • There are many programming languages, but they usually fall into two categories • High-level languages are usually machine-independent and instructions are often more expressive • C, Fortran, Pascal, Basic • Low-level languages are usually machine-specific and offer much finer-grained instructions that closely match the machine language of the target processor • Assembly languages for MIPS, x86 CMPE 325Ch. #3

  10. Assembly Languages • Assembly languages are text representations of the machine language • One statement represents one machine instruction • Abstraction layer between high-level programs and machine code CMPE 325Ch. #3

  11. Machine Language • Machine language is the native language of the computer • The words are called instructions • The vocabulary is the instruction set • Bit representation of machine operations to be executed by the hardware • We will focus on the MIPS instructions • Other RISC-based instruction sets are similar • Different instruction sets tend to share a lot of commonalities since they function similarly CMPE 325Ch. #3

  12. Fitting Languages Together temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; High Level Language Program Compiler lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) Assembly Language Program Assembler 0000 1001 1100 0110 1010 1111 0101 1000 1010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111 Machine Language Program Machine Interpretation Control Signal Specification High/Low on control lines CMPE 325Ch. #3

  13. Assembly Instructions • The basic type of instruction has four components: • Operator name • Place to store result • 1st operand • 2nd operand add dst, src1, src2 • Simple, fixed formats make hardware implementation simpler (“simplicity favors regularity”) • On most architectures, there are no restrictions on elements appearing more than once CMPE 325Ch. #3

  14. Assembly Instructions Assembly Language Instruction Format:      a) [label:] operation [operand1 [operand2 [operand3]]] [ # [comment]] b) Labels A symbol string associated with a specific memory address      c) Operations:            1) Assembler directive 2)    Machine instruction      d) Operands:            1) Register names (i.e. $0, $29, named: $a0, 0($t0)),            2) Immediate value Numeric expression 3) Address label (instruction or data, i.e. Loop2:, myVal:)      e) Comments: Text string from # symbol to end of line. Ignored by assembler. CMPE 325Ch. #3

  15. Arithmetic Operators • Consider the C operation for addition a = b + c; • Use the add operator in MIPS add a, b, c • Use the sub operator for a=b–c in MIPS sub a, b, c • Since assembly code can be difficult to read, the common practice is to use # for comments CMPE 325Ch. #3

  16. Complex Operations • What about more complex statements? a = b + c + d - e; • Break into multiple instructions add t0, b, c # t0 = b + c add t1, t0, d # t1 = t0 + d sub a, t1, e # a = t1 - e • Compilers often use temporary variables when generating code • Notice all of the comments! CMPE 325Ch. #3

  17. Data Representation • Bits: 0 or 1 • Bit strings – sequence of bits • 8 bits is a byte • 16 bits is a half-word • 32 bits is a word • 64 bits is a double-word • Characters – one byte, usually using ASCII • Integer numbers – stored in 2’s complement (reviewed in the next chapter) • Floating point – uses a mantissa and exponential m  2e (also covered in the next chapter) CMPE 325Ch. #3

  18. Data Storage • In high-level programs we store data in variables • In practice, where is this data stored? • The answer is that it can be stored in many different places • Registers • Cache (RAM or disk) • Random Access Memory (RAM) • Disk CMPE 325Ch. #3

  19. Register Organization • Register organization is one of the defining aspects about a particular processor architecture • Three basic mechanisms for operators/operands • Accumulator – architecture which uses a single register for one of the sources and the destination (ex. 8088) • Stack – operands are pushed and popped (ex, Intel MP) • General Purpose – a limited number of registers used to store data for any purpose (ex. most systems today) • A register is a small high-speed block of memory that holds data • We will focus in this course on general purpose CMPE 325Ch. #3

  20. Accumulator Example • Consider the code a = b + c; • In an accumulator-based architecture load addressB add addressC store addressA CMPE 325Ch. #3

  21. General Purpose Registers • When using General Purpose Registers (GPRs), data can access in different ways • Load-Store (L/S) – data is loaded into registers, operated on, and stored back to memory (ex. all RISC instruction sets) • Hardware for operands is simple • Smaller is faster since clock cycle can be kept short  Emphasis is on efficiency • Memory-Memory – operands can use memory addresses as both a source and a destination (ex. Intel) CMPE 325Ch. #3

  22. MIPS Architecture • MIPS is a load-store architecture • Each register is 32 bits (word) wide • The MIPS has 32 general purpose registers (some reserved for specific purposes) • MIPS also has 32 floating point only registers CMPE 325Ch. #3

  23. Register Naming • Registers are identified by a $<num> • By convention, we also give them names • $zero contains the hardwired value 0 • $s0, $s1, … $s7 are for save values • $t0, $t1, … $t9 are for temp values • The others will be introduced as appropriate • Compilers use these conventions to make linking a smooth process • Unlike variables, there are a fixed number of data registers (“smaller is faster”) CMPE 325Ch. #3

  24. Using registers • Goals • Keep data in registers as much as possible • Always use data still in registers if possible • Issues • Finite number of registers available • Spill registers to memory when all registers in use • Data must also be stored across procedures • Arrays • Data is too large to store in registers • Need to compute index • Dynamic memory allocation • Dynamically allocated data structures must be loaded one word at a time CMPE 325Ch. #3

  25. Arithmetic Operators: II • Consider the C operation for addition where the variables are in $s0-$s2 respectively a = b + c; • The add operator using registers add $s0, $s1, $s2 # a = b + c • Use the sub operator for a=b–c in MIPS sub $s0, $s1, $s2 # a = b - c CMPE 325Ch. #3

  26. Complex Operations: II • What about more complex statements? a = b + c + d - e; • Break into multiple instructions add $t0, $s1, $s2 # $t0 = b + c add $t1, $t0, $s3 # $t1 = $t0 + d sub $s0, $t1, $s4 # a = $t1 - e CMPE 325Ch. #3

  27. Constants • Often want to be able to add a constant • Use the addi instruction addi dst, src1, immediate • The immediate is a 16 bit value CMPE 325Ch. #3

  28. Constant Example • Consider the following C code a++; • The addi operator addi $s0, $s0, 1 # a = a + 1 CMPE 325Ch. #3

  29. MIPS Simple Arithmetic Instruction Example Meaning Comments add add $1,$2,$3 $1 = $2 + $3 3 operands; Exceptions subtract sub $1,$2,$3 $1 = $2 – $3 3 operands; Exceptions add immediate addi $1,$2,100 $1 = $2 + 100 + constant; Exceptions add unsigned addu $1,$2,$3 $1 = $2 + $3 3 operands; No exceptions subtract unsign subu $1,$2,$3 $1 = $2 – $3 3 operands; No exceptions add imm unsign addiu $1,$2,100 $1 = $2 + 100 + constant; No exceptions CMPE 325Ch. #3

  30. Putting Data in Registers • Data transfer instructions are used to move data to and from memory in load-store • A load operation moves data from memory to a register and a store operation moves data from a register to memory • One word at a time is loaded from memory to a register on MIPS using the lw instruction • Load instructs have three parts • Operator name • Destination register • Base register address and constant offset lw dst, offset(base) • Offset value is signed (use ulw for unsigned) CMPE 325Ch. #3

  31. Immediate Registers Data to load/ location to store into Memory + Base Memory Access • All memory access happens through loads and stores • Aligned words, halfwords, and bytes • Floating Point loads and stores for accessing FP registers • Displacement based addressing CMPE 325Ch. #3

  32. Loading Data Example • Consider the example a = b + *c; • Use the lw instruction to load lw $t0, 0($s2) # $t0 = Memory[c] add $s0, $s1, $t0 # a = b + *c CMPE 325Ch. #3

  33. Accessing Arrays • Arrays are really pointers to the base address in memory • Use offset value to indicate which index • Remember that addresses are in bytes, so multiply by the size of the element • Consider an integer array where A is the base address • The data to be accessed is at index 5 • Then the address from memory is A + 5 * 4 • Unlike C, assembly does not handle pointer arithmetic for you! CMPE 325Ch. #3

  34. Array Example • Consider the example a = b + c[9]; • Use the lw instruction offset lw $t0, 36($s2) # $t0 = Memory[c[9]] add $s0, $s1, $t0 # a = b + c[9] CMPE 325Ch. #3

  35. Complex Array Example • Consider the example a = b + c[i]; • First find the correct offset add $t0, $s3, $s3 # $t0 = 2 * i add $t0, $t0, $t0 # $t0 = 4 * i add $t1, $s2, $t0 # $t1 = c + 4*i lw $t2, 0($t1) # $t2 = Memory[c[i]] add $s0, $s1, $t2 # a = b + c[i] • Note: Multiply will be covered later CMPE 325Ch. #3

  36. Storing Data • Storing data is just the reverse and the instruction is nearly identical • Use the sw instruction to copy a word from the source register to an address in memory sw src, offset(base) • Offset value is signed (usw for unsigned) CMPE 325Ch. #3

  37. Storing Data Example • Consider the example *a = b + c; • Use the sw instruction to store add $t0, $s1, $s2 # $t0 = b + c sw $t0, 0($s0) # Memory[s0] = b + c CMPE 325Ch. #3

  38. Storing to an Array • Consider the example a[3] = b + c; • Use the sw instruction offset add $t0, $s1, $s2 # $t0 = b + c sw $t0, 12($s0) # Memory[a[3]] = b + c CMPE 325Ch. #3

  39. Complex Array Storage • Consider the example a[i] = b + c; • Use the sw instruction offset add $t0, $s1, $s2 # $t0 = b + c add $t1, $s3, $s3 # $t1 = 2 * i add $t1, $t1, $t1 # $t1 = 4 * i add $t2, $s0, $t1 # $t2 = a + 4*i sw $t0, 0($t2) # Memory[a[i]] = b + c CMPE 325Ch. #3

  40. MIPS Load/Store Instruction Example Meaning Comments store word sw $1, 8($2) Mem[8+$2]=$1 Store word store half sh $1, 6($2) Mem[6+$2]=$1 Stores only lower 16 bits store byte sb $1, 5($2) Mem[5+$2]=$1 Stores only lowest byte store float sf $f1, 4($2) Mem[4+$2]=$f1 Store FP word load word lw $1, 8($2) $1=Mem[8+$2] Load word load halfword lh $1, 6($2) $1=Mem[6+$2] Load half; sign extend load half unsign lhu $1, 6($2) $1=Mem[8+$2] Load half; zero extend load byte lb $1, 5($2) $1=Mem[5+$2] Load byte; sign extend load byte unsign lbu $1, 5($2) $1=Mem[5+$2] Load byte; zero extend load float lf $f1, 4($2) $f1=Mem[4+$2] Load FP register CMPE 325Ch. #3

  41. Memory Addressing • Almost all architectures support byte addressing as well as word addressing • Different architectures have different ways of ordering the bits, known as the byte order • Some architectures limit the way data is stored so as to improve efficiency CMPE 325Ch. #3

  42. Byte Ordering • Two basic ways of ordering bits • Big Endian – the “big” end comes first and the most significant bit (MSB) is the lowest memory address • Little Endian – the “little end” comes first and the least significant bit (LSB) is the first address (ex. Intel) • Some systems such as MIPS and PowerPC can do both, but are primarily big endian Little Endian byte 0 3 2 1 0 msb lsb 0 1 2 3 Big Endian byte 0 CMPE 325Ch. #3

  43. Byte Ordering Example • Consider the following word (32 bits) of memory • Big endian interprets as AB CD 00 00 (2882338816) • Little endian interprets as 00 00 CD AB (52651) Little Endian LSB Little Endian MSB Big Endian MSB Big Endian LSB AB CD 00 00 MemoryAddress 0 1 2 3 CMPE 325Ch. #3

  44. 0 1 2 3 Aligned Not Aligned Alignment Restrictions • In MIPS, data is required to fall on addresses that are even multiples of the data size • Consider word (4 byte) memory access 0 4 8 12 16 0 4 8 12 16 CMPE 325Ch. #3

  45. Assembly Language Programming EnvironmentMIPS Assembly Language Syntax:a)       Numbers are base 10b)       Hex numbers are preceded “0x”.c)       Special string characters: 1) newline \n 2) tab \t 3) quote \”d)       Labels are followed by “:”e)       Identifiers begin with letter and may contain alphanumeric, underscore, and dots.f)        Keywords: Instruction opcodes can not be used as identifiers.g)       Comments begin with a “#” symbols and run to end-of-line.h)       Assembly language statements cannot be split across multiple lines. CMPE 325Ch. #3

  46. Assembly Language ProgramsExample w/basic elements:# Program name, description and comments .data # data segment item: .word 10 # define/name a variable and initial value .text # code segment .globl main # must be global; main: # your code goes here lw $t0, item li $v0, 10 # exit to kernel syscall .end CMPE 325Ch. #3

  47. Assembly Language Conventions:SPIMAssembler Directives: .data Subsequent data items stored in user(kernel) data segment(.kdata) .text Subsequent items are stored in user(kernel) text segment (.ktext) .asciiz str Store ascii string in memory and zero terminate .word w1,… Store 32 bit words in memory .half h1,… Store 16 bit half-words in memory .byte b1,… Store 8 bit bytes in memory .double d1,… Store 64 bit words in memory .space nbytes Allocate nbytes of space in current segment .globl sym, Declare label sym global. Can be referenced from other files .align n Align next datum on a 2^n boundary CMPE 325Ch. #3

  48. Assembly Language Instructions: MIPS Instruction classes and format conventions:MIPS Core Instructions Operation Operands Size/ClocksAdd: add Rd, Rs, Rt 1/1Add Immediate: addi Rt, Rs, Imm 1/1Add Immediate Unsigned: addiu Rt, Rs, Imm 1/1Add Unsigned: addu Rd, Rs, Rt 1/1And: and Rd, Rs, Rt 1/1And Immediate: andi Rt, Rs, Imm 1/1Branch if Equal: beq Rs, Rt, Label 1/1Branch if Not Equal: bne Rs, Rt, Label 1/1Jump: j Label 1/1Jump and Link: jal Label 1/1Jump Register: jr Rs 1/1Load Byte: lb Rt, offset(Rs) 1/1Load Byte Unsigned: lbu Rt, offset(Rs) 1/1Load Upper Immediate: lui Rt, Imm 1/1Load Word: lw Rt, offset(Rs) 1/1Or: or Rd, Rs, Rt 1/1Or Immediate: ori Rt, Rs, Imm 1/1Set on Less Than: slt Rd, Rt, Rs 1/1Set on Less Than Immediate: slti Rt, Rs, Imm 1/1Set on Less Than Immediate Unsigned: sltiu Rt, Rs, Imm 1/1Set on Less Than Unsigned: sltu Rd, Rt, Rs 1/1Shift Left Logical: sll Rd, Rt, sa 1/1Shift Right Logical: srl Rd, Rt, sa 1/1Subtract: sub Rd, Rs, Rt 1/1Subtract Unsigned: subu Rd, Rs, Rt 1/1Store Byte: sb Rt, offset(Rs) 1/1Store Word: sw Rt, offset(Rs) 1/1MIPS Arithmetic Core Instructions Operation Operands Size/ClocksDivide: div Rs, Rt 1/38Divide Unsigned: divu Rs, Rt 1/38Move From High: mfhi Rd 1/1Move From Low: mflo Rd 1/1Multiply: mult Rs, Rt 1/32 Multiply Unsigned: multu Rs, Rt 1/32 CMPE 325Ch. #3

  49. Assembly Language Instruction: (cont)MIPS I Instructions (remaining) Operations Operands Size/ClocksBranch if Greater Than or Equal to Zero: bgez Rs, Label 1/1Branch if Greater Than or Equal to Zero and Link: bgezal Rs, Label 1/1Branch if Greater Than Zero: bgtz Rs, Label 1/1Branch if Less Than or Equal to Zero: blez Rs, Label 1/1Branch if Less Than Zero and Link: bltzal Rs, Label 1/1Branch if Less Than Zero: bltz Rs, Label 1/1Cause Exception: break 1/1Exclusive Or: xor Rd, Rs, Rt 1/1Exclusive Or Immediate: xori Rt, Rs, Imm 1/1Jump and Link Register: jalr Rd, Rs 1/1Load Halfword: lh Rt, offset(Rs) 1/1Load Halfword Unsigned: lhu Rt, offset(Rs) 1/1Load Word Left: lwl Rt, offset(Rs) 1/1Load Word Right: lwr Rt, offset(Rs) 1/1Move to High: mthi Rs 1/1Move to Low: mtlo Rs 1/1Nor: nor Rd, Rs, Rt 1/1Return from Exception rfe 1/1Shift Left Logical Variable: sllv Rd, Rt, Rs 1/1Shift Right Arithmetic: sra Rd, Rt, sa 1/1Shift Right Arithmetic Variable: srav Rd, Rt, Rs 1/1Shift Right Logical Variable: srlv Rd, Rt, Rs 1/1Store Halfword: sh Rt, offset(Rs) 1/1Store Word Left: swl Rt, offset(Rs) 1/1Store Word Right: swr Rt, offset(Rs) 1/1System Call: syscall 1/1Operands            1) Register names Rd, Rs, Rt (d=destination, s=source, t=second source/dest)            2) Immediate value Imm, sa, offset (Numeric expr= 16 bits,shift amount, offset) 3) Address label Label(28 or 16 bits) CMPE 325Ch. #3

  50. Assembly Language Instruction: (cont)Pseudo Instructions Operations Operands Size/ClocksAbsolute Value: abs Rd, Rs 3/3Branch if Equal to Zero: beqz Rs, Label 1/1Branch if Greater Than or Equal : bge Rs, Rt, Label 2/2Branch if Greater Than or Equal Unsigned: bgeu Rs, Rt, Label 2/2Branch if Greater Than: bgt Rs, Rt, Label 2/2Branch if Greater Than Unsigned: bgtu Rs, Rt, Label 2/2Branch if Less Than or Equal: ble Rs, Rt, Label 2/2Branch if Less Than or Equal Unsigned: bleu Rs, Rt, Label 2/2Branch if Less Than: blt Rs, Rt, Label 2/2Branch if Less Than Unsigned: bltu Rs, Rt, Label 2/2Branch if Not Equal to Zero: bnez Rs, Label 1/1Branch Unconditional: b Label 1/1Divide: div Rd, Rs, Rt 4/41Divide Unsigned: divu Rd, Rs, Rt 4/41Load Address: la Rd, Label 2/2Load Double: ld Rd, Label 2/2Load Immediate: li Rd, value 2/2Move: move Rd, Rs 1/1Multiply: mul Rd, Rs, Rt 2/33Multiply (with overflow exception): mulo Rd, Rs, Rt 7/37Multiply Unsigned (with overflow exception): mulou Rd, Rs, Rt 5/35 CMPE 325Ch. #3

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