FPGA Calculator Core

1. FPGA Calculator Core Final Presentation Chen Zukerman LiranMoskovitch Advisor : Moshe Porian Duration: semesterial December 2012

2. Contents • Project Overview • Top Architecture • Micro Architecture • Testability • Synthesis Results • Hardware Debugging • Project Educational Value • Project Movie • Lab Demo • Projecteducationalvalue

3. Project Overview 0.5 • Hardware implementation of calculator core : • Positive integers • Operands: ‘+’ , ’-’ , ’x’, ‘^’ , ‘ { ‘ , ‘ } ‘ • Precedence rules compatible • Manually acquisition Input via Matlab GUI • Result display + debugging feedback on GUI screen חן FPGA Calculator Core Result

4. Top Architecture 0.5 חן Altera Cyclone II FPGA • Wishbone Intercon Uart In 115200 bits/sec WBS3 CALC_CORE GUI - MATLAB WBM3 Uart Out 115200 bits/sec RX PATH WBM1 WBS1 TX PATH WNB2 Sys_clk, 100[MHZ] integrated WBS2 Clock & Reset FPGA Clock, 50[MHZ] Implemented Sys_reset FPGA Reset

5. Data Flow 1.5 חן Postfix Data . . FF SOF SOF Altera Cyclone II FPGA Type Wishbone Intercon Type Type Type Address Address Address Address Infix - Data . . FF Data Length Data Length Data Length Data Length WBS3 CALC_CORE Result Postfix Data . . FF Result Result CRC GUI - MATLAB WBM3 Uart In 115200 bits/sec EOF Infix - Data . . FF Uart Out 115200 bits/sec RX PATH WBM1 CRC EOF WBS1 TX PATH WNB2 Sys_clk, 100[MHZ] WBS2 Clock & Reset FPGA Clock, 50[MHZ] Sys_reset integrated FPGA Reset Implemented

6. Micro Architecture 0.5 חן

7. Calculator Core in action detailed view 02 00 07 03 00 03 07 1.5 חן 09 82 09 0A 09 09 09 0A 0A 09 0A 0A 0A 0A 09 82 1 1 1 1 1 09 82 0A 00 5A FF FF FF 5A 5A 5A 5A 5A 00 00 00

8. Testability 0.5 • Multi-Level testing environments were implemented • Top Level Testing and simulating environment : חן PLL BYPASS Goals : functionality verification (in system boundaries) verification that hardware and software calculation results are equal

9. PLL Vs. PLL Bypass 1.5 חן • The top level contains PLLunit that produces system clock • Simulating The top level with PLL unit is slow • PLL BYPASS • Disables PLL unit and produce system clock manually • Implemented one hierarchy above the PLL unitin order to get faster simulation time (if … generate) • Choosing between PLL and PLL BYPASS is done by genericsim_clk_gen_g (if true – PLL is disabled, otherwise enabled)

10. GUI Exercise display 0.5 לירן Exhibit the data to transmit Method select Hardware result Software result Gui messages Enter the exercise

11. GUI - Capabilities 1 לירן • Operationalfeatures: • Receive data from the user • Data abstraction – easy and simple operation • Generates only correct packets with legal values • Method choosing. • Debug features: • Transferred data display • Messages display • Generatestextfilesavailableforsimulation

12. Operation Table 0.5 לירן

13. Text Files 0.5 Calculation string txt file format : חן • Data line - full packet calculation string • General comment – desired test literally, explanation, Clarifications etc. • Different notations comment: infix , postfix , postfix in hex + operator conversion Result string txt file format : • Data line – full packet expected result string • Comment : infix notation + result [hex] • General comment – desired test literally, explanation, Clarifications etc. TGD – data length ADR – Client inner address TGA – Client Type Wishbone signals Postfix data Wishbone signals Infix data EOF CRC SOF Expected result End of postfix End of infix EOF SOF CRC

14. TextFile 0.5 • Calculation string txt file example (4 strings): חן

15. String generator + checker 0.5 חן • Allows simple & fast testing and simulation • Working with multiple strings one after the other • Automatic feedback – message in the transcript window

16. String generator + checker example 1 חן Full packet calculation string Full packet result string String Generator closes the input txt file End of successful top level test String Generator opens the input txt file String Generator and Checker simulation reports – Transcript Window

17. Adder basic tests: Test Plan 1.5 • For simulation and hardware as well לירן • Blocks Basic Tests (inputs/outputs limits and special cases): Multiplier basic tests: • General Tests (inputs/outputs limits and special cases): • Simple string using each operator once • Strings using same operator all along • Strings using different operator in the beginning of the string • Each operator used twice in a single string • Short string • Long string • Brackets testing (in different location along the string) • Bigger\Smaller Right\Left Operand Subtractor basic tests: Power basic tests:

18. Synthesis Results 0.5 חן

19. Max Frequency 0.5 חן • Required frequency : 100 [MHz] • Actual Max frequency : 133.87 [MHz]

20. Hardware Debugging 1.5 חן • Problem: first programming on FPGA … nothing happens (GUI does not receive the returned full packet result string) . • Source : The reset button on the DE2 board is active low while the PLL reset polarity (predefined by the MegaWizard) is active high . • Solution : adding the pll_reset signal which insures, that when the FPGA reset button is active ('0'), the PLL reset would be active as well with the appropriate polarity ('1') . • Conclusion : • Fundamental principle - system synthesis MUST come only AFTER successful simulation - Early detection of the problem . • MegaWizard PLL RESET (areset) is always active high ('1'). Special attention should be paid to the reset polarity issue . • Programming indication led could be useful .

21. Project Educational Value 1.5 • Planning and Specifying a Project • Writing reusable generic code • Profound acquaintance with communication protocols : UART, Wishbone • Integration of many components • Verifying logic correctness using smart simulators, waveforms, text files and scripts (do files) • Using the GUI for hardware Testing and also as a producer of text files which are used later by the smart simulators • Documentation of the work done • SVN is a very useful tool • Seriousness, Persistence, spending time and a will to learn and understand are a Guarantee of success  חן

22. Project Movie http://www.youtube.com/watch?v=0POkQuCi9Tk

23. Lab Demo