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# ECE 448 FPGA and ASIC Design with VHDL - PowerPoint PPT Presentation

Lab 1 Introduction to Aldec Active HDL Implementing Combinational Logic in VHDL. ECE 44 8 – FPGA and ASIC Design with VHDL. George Mason University. Part 1. Introduction to Aldec Active-HDL. Example: Seven Segment Encoder. S6. S5. S4. S3. S2. S1. S0. DP. Experiment 1

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Presentation Transcript

Introduction to Aldec Active HDL

Implementing Combinational

Logic in VHDL

ECE 448 – FPGA and ASIC Design with VHDL

George Mason University

Introduction to Aldec Active-HDL

Example: Seven Segment Encoder

S5

S4

S3

S2

S1

S0

DP

Problem 1

ALU of Motorola 68HC11

Accumulators A and B or

A

B

7

0

7

0

D

Double Accumulator D

0

15

X-index register

IX

0

15

Y-index register

IY

0

15

Stack Pointer

SP

0

15

Program Counter

PC

0

15

Condition Code Register

CCR

7

0

S X H I N Z V C

CCR

7

0

S X H I N Z V C

carry / borrow

overflow

zero

negative

half-carry (from bit 3)

stop disable

Zero flag - Z

zero result

Z = 1 if result = 0

0 otherwise

Negative flag- N

negative result

N = sign bit of the result

R7 - for an 8-bit result

Carry flag - C

out-of-range for unsigned numbers

C = 1 if result > MAX_UNSIGNED or

result < 0

0 otherwise

where MAX_UNSIGNED = 28-1

for 8-bit results

Overflow flag - V

out-of-range for signed numbers

V = 1 if result > MAX_SIGNED or

result < MIN_SIGNED

0 otherwise

where MAX_SIGNED = 27-1 and

MIN_SIGNED = -27

for 8-bit results

Indication of overflow

Negative

+ Negative

= Positive

Positive

+ Positive

= Negative

Immediate mode

A + \$5C  A

Direct mode

A+ (\$001B)  A

Extended mode

A + (\$6D00)  A

M

Indexed mode

A+(IX+\$56)  A

A+(IY+\$56)  A

Assembly language

mnemonic [operands]

NEGB

Machine code

opcode [operands]

\$50

\$8B \$4A

\$BB \$5B \$78

N Z V C

1. addition Acc + M  Acc

2. subtraction Acc – M  Acc

SUB [A, B]

SBC [A, B]

IMM, DIR, EXT, IND

IMM, DIR, EXT, IND

3. negation -X

NEG [A, B]

NEG

INH

EXT, IND

N Z V C

1. addition A + B  A

ABA

2. subtraction A – B  A

SBA

INH

INH

• unsigned multiplication

• A x B  D

• MUL

– – –

INH

Mini ALU

4

4

A

4

Mini ALU

4

R

B

4

M

To use arithmetic operations involving

std_logic_vectors you need to include the

following library packages:

library ieee;

use ieee.std_logic_1164.all;

use ieee.STD_LOGIC_UNSIGNED.ALL;

You can use standard +, - operators

signal A : STD_LOGIC_VECTOR(3 downto 0);

signal B : STD_LOGIC_VECTOR(3 downto 0);

signal C : STD_LOGIC_VECTOR(3 downto 0);

……

C<= A + B;

Problem 2

Variable Rotator

Part 3

Variable rotator

C = A <<< B

A – 16-bit data input

B - 4-bit rotation amount

A

16

4

B

16

C

A(0)

Fixed Rotations in VHDL

A<<<1

A(3)

A(2)

A(2)

A(1)

A(0)

A(3)

A_rotL <= A(2 downto 0) & A(3)