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AT91SAM7 L Enhanced Embedded Flash Controller (EEFC)

AT91SAM7 L Enhanced Embedded Flash Controller (EEFC). EEFC Features. 64KB or 128KB single plane memory organized in several pages 128-bit wide interface Two 128-bit buffers for code read acceleration in sequential access One write buffer for page programming Write buffer size  Page size

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AT91SAM7 L Enhanced Embedded Flash Controller (EEFC)

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  1. AT91SAM7LEnhanced Embedded Flash Controller (EEFC)

  2. EEFC Features • 64KB or 128KB single plane memory organized in several pages • 128-bit wide interface • Two 128-bit buffers for code read acceleration in sequential access • One write buffer for page programming • Write buffer size  Page size • One lock bit per lock region • General purpose NVM bits • Controls specific features in the device including Hardware Security Protection

  3. Embedded Flash Organization • 128KB Flash • 512 pages of 256 bytes • 8 lock regions of 16KB • Single plane • 64KB Flash • 256 pages of 256 bytes • 16 lock regions of 4KB • Single plane

  4. Embedded Flash Performance • Embedded Flash Wait State (VDDCORE @1.80V) • 0 wait state single cycle access up to 17.2MHz • 1 wait state up to 30MHz • 3 wait states up to 39.7MHz • 10ms Full Chip Erase • 2.3ms Page Programming Time • 4.6ms Page Programming Time including auto-erase

  5. Sequential Code Read Acceleration • Two 128-bit prefetch buffers to optimize sequential Code Fetch in ARM mode • In case of sequential reads, the first access takes 4 cycles, the other ones only 1 cycle 3WS

  6. Flash Commands

  7. Embedded Flash Descriptor • Command Get Flash Descriptor (GETD) allows to learn the Flash organization • Suitable for software adaptability when migrating to higher Flash density • Read Flash Result Register (MC_FRR) after writing the GETD command to get Flash information • MC_FRR • First read – Word 0 – FL_ID (Get Flash ID) • Second read – Word 1 – FL_SIZE (Get Flash Size) • Third read – Word 2 – FL_PAGE_SIZE (Get Flash Page Size) • …

  8. NVM Bits • Lock bits protect lock regions from being written or erased by inadvertence • 8 lock bits for the 128KB Flash (16KB) • 16 lock bits for the 64KB Flash (4KB) • General Purpose NVM Bits • GPNVM0 enables the Security Bit • GPNVM1 defines the boot mode selection (Flash or BootROM) • No more GPNVM bits for the BOD !

  9. What’s New? • 128-bit wide memory bus • No FMCN initialization, only FWS must be configured • Zero Wait State up to 17.2MHz • Sequencial code read acceleration in ARM mode • New commands • Get Flash Descriptor, Get Lock Bit Status, Get GPNVM Bit Status associated with the Flash Result Register • No dedicated command to enable the security bit but GPNVM bit instead • No NVM bits for BOD

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