REGISTER MANAGMENT TOOL

1. REGISTER MANAGMENT TOOL Final presentation – Part B Preformed by: Liat Honig Nitzan Carmel Supervisor: Moshe Porian Date: 17/05/13 Duration: Two Semesters

2. Many teams need to create their own register blocks for FPGA systems. Leading to BUGS Double Effort The Solution a Register Management Tool Automatically generates registers according to a required specification using a smart interface!

3. AutoReg – a smart register management tool Insert your project’s specifications to the GUI Automatically create VHD and HSID for register blocks!

4. The Solution – a Register Management Tool Project Goals • Automatically generates registers according to the required • specification. • Determine and characterize a local bus for communication with all the register slave blocks. • Generic Implementation that allows reuse in multiple projects. • Encapsulation of implementation, which will be hidden from the user. • Enables REUSE • Creates unity in the registers VHD files • Saves money and resources

5. The Solution – a Register Management Tool Project Goals • Determine and characterize a local bus for communication with all the register slave blocks. • Generic Implementation that allows reuse in multiple projects. • Encapsulation of implementation, which will be hidden from the user. • Creates documentation for the components created • Leads to an organized –HSID • Alarms in case of incorrect input • Manages the registers through the entire project

6. Project Goals • Determine and characterize a local bus for communication with all the register slave blocks. • Generic Implementation that allows reuse in multiple projects. • Encapsulation of implementation, which will be hidden from the user.

7. Project Specifications • 1. Writing a GUI interface through which the user will determine a variety of attributes. • 2. Interactivity - The tool will provide feedbackfor user errors and will provide a summary output. VHD files Local Bus Master Simulation Environment • 3. VHDL: • 4. No special license will be needed to operate the tool, an EXE file will be given to the user. • 5. HSID will be generated under IEEE standards (IP-XACT)

8. Project Steps • 1. Determine the implementation platform of the user • interface and data processing: Excel/MATLAB/C++/C#/JAVA . • 2. Full characterization of the tool capabilities. • 3. Learning the working environment (Wishbone protocol, • advanced VHDL coding , MODELSIM simulation environment). • 4. VHDL generic design and simulation. • 5. Implementing the GUI (Graphic User Interface) • 6. Implementing Automatic VHDL generation. • 7. Final MODELSIM and MATLAB Simulations.

9. VHDL Implementation

10. General Description Project Goals • Determine and characterize a local bus for communication with all the register slave blocks. • Generic Implementation that allows reuse in multiple projects. • Encapsulation of implementation, which will be hidden from the user. Register Register Register Block Block Local Bus Register access Block Chip data I/O

11. VHDL Top Architecture Project Goals Block A reset clk Block_A_reg_top • Determine and characterize a local bus for communication with all the register slave blocks. • Generic Implementation that allows reuse in multiple projects. • Encapsulation of implementation, which will be hidden from the user. Function_1 Reg_status_1 Function_2 Reg_enable_2 Wishbone Master Function_3 func_err_3

12. Reg Block Architecture Functional Block Block_A_reg_top Inputs from block • Determine and characterize a local bus for communication with all the register slave blocks. • Generic Implementation that allows reuse in multiple projects. • Encapsulation of implementation, which will be hidden from the user. Reg1 WB Slave WB Master Outputs to block Reg2 Priority Encoder Reg3 4 reg_chosen Reg4 Data from chosen register

13. Generic Implementation

14. Generic Implementation

15. VHDL Simulation

16. Simulation Environment Macro Scripts

17. Simulation Environment Test Bench Macro Scripts • Compilation • Simulation • Waveforms

18. Simulation Environment Results Output File Simulation input Simulation outputs Test Bench Macro Scripts Waveforms • Procedure called serially many times • Comparison to expected values • Reporting results to output file • Compilation • Simulation • Waveforms

19. Test Plan - Overview • Testing small modules separately • gen_reg.vhd: • Read • Write • Read/Write • Clear On Read • Const. • wbs_reg.vhd • Read transactions (single/burst) • Write transactions (single/burst) • encoder_generic.vhd • Then, testing the entire design • Gen_block.vhd

20. Test Plan – Cases • Testing Regular Activity • Various generic values for address width • Various values for data • Read/Write single/burst wishbone cycles for suitable registers • Testing system boundaries • Testing system generics

21. Synthesis

22. Synthesis Results • A synthesis demonstration was ran, using QuartusII 12.0sp2, using the following test case: 32 registers, with 8-bit data width, with device EP4CGX50DF27C6 • Compilation and Synthesis finished successfully. • Summaries: • Maximum Frequencies: • Slow 1.2V 85C model – 1199MHz • Slow 1.2V 0C model – 1328MHz

23. Netlists

24. Graphical User Interface

25. Requirements from GUI • Easy to use user experience • Feedback is provided in real time • Data is filled automatically if possible • Easy project view and management • Data and Address can be represented in both Hexadecimal and Decimal formats

26. Opening Screen – project settings Settings made for the entire project Browser for finding the requested directory Choose a protocol Specify address width Choose address radix Specify data width Choose data radix Specify number of blocks Specify a directory to save the generated files

27. Opening Screen – project settings Settings made for the entire project Choose a protocol Specify address width Choose address radix Specify data width Choose data radix Specify number of blocks Specify a directory to save the generated files Continue to next screen

28. 2nd Screen – Edit Block settings Settings made for the specific block Opens text editor Specify a name Provide a description (optional)

29. 2nd Screen – Edit Block settings Settings made for the specific block Specify a name Provide a description (optional) Specify an initial address Specify number of registers choose reset polarity Navigation tree view delete current block Continue to next screen back to project settings

30. 3rd screen – Edit register settings Settings made for a specific register Specify a name Provide a description Choose register type Specify the offset address Specify the initial data value Back to block settings delete current register Navigation tree view

31. 3rd screen – Edit register settings Settings made for a specific register Specify a name Provide a description Choose register type Specify the offset address Specify the initial data value

32. Top menus • File menu Create a new project Open an existing project Save project as Save current project Close current project Exit AutoReg • Help menu About AutoReg Open user guide • Generate menu Report for errors Generate VHDL files

33. Tree View • “Top View” of the entire project • Automatically sorted by the absolute address • Allows easy navigation between all the screens and components • Addresses and names are filled automatically • Navigation is blocked when errors or missing data is found in the current window

34. Errors Display AutoReg notifies the user and prevents access to some contents in the project whenever: Addresses/bits are overlapping Before Deleting an object Data isn’t legal/valid/complete • Easy to use user experience • Feedback is provided in real time

35. Outputs

36. Error Report

37. HSID

38. XML – according to IP-XACT standard

39. VHD files • VHD files and reports are created in two sub-folders:

40. DEMO

41. Suggestions for a later project • An option to create a wide register (more than one address). • Support other protocols (not wishbone only) • Support more register types • Add a possibility to mix between the bits of the same register when it comes to access manners. • Support boards and not just on FPGA • Search and filter possibilities • Copy-Paste possibilities

42. Suggestions for a later project • 8. Creating a database with options to import and export • 9. An option to duplicate , add or delete a register using a right-click option from the tree view. • 10. Unifying the edit_block figure and the edit_reg figure to prevent window from “jumping” • 11. Under the help menu, add a keyboard map for all keyboard shortcuts of the GUI. • Link: AutoRegGui - other features.docx

43. The End