CMPUT680 - Fall 2003

1. CMPUT680 - Fall 2003 Topic B: Open Research Compiler José Nelson Amaral http://www.cs.ualberta.ca/~amaral/courses/680 CMPUT 680 - Compiler Design and Optimization

2. Logical Compilation Model driver (sgicc/sgif90/sgiCC) front end + IPA (gfec/gfecc/mfef90) back end (be) linker (ld) WHIRL (.B/.I) obj (.o) Src (.c/.C/.f) a.out/.so Data Path Fork and Exec CMPUT 680 - Compiler Design and Optimization

3. Components of Pro64 Front end Interprocedural Analysis and Optimization Loop Nest Optimization and Parallelization Global Optimization Code Generation CMPUT 680 - Compiler Design and Optimization

4. Data Flow Relationship Between Modules -O3 -IPA LNO Local IPA Main IPA Lower to High W. .B Inliner gfec .I lower I/O gfecc (only for f90) .w2c.c WHIRL C f90 .w2c.h .w2f.f WHIRL fortran -O0 Take either path Lower all CG Very high WHIRL -phase: w=off High WHIRL Main opt Lower Mid W -O2/O3 Mid WHIRL Low WHIRL CMPUT 680 - Compiler Design and Optimization

5. Front Ends • C front end based on gcc • C++ front end based on g++ • Fortran90/95 front end from MIPSpro CMPUT 680 - Compiler Design and Optimization

6. Intermediate Representation IR is called WHIRL • Common interface between components • Multiple languages and multiple targets • Same IR, 5 levels of representation • Continuous lowering as compilation progresses • Optimization strategy tied to level CMPUT 680 - Compiler Design and Optimization

7. IPA Main Stage Analysis • alias analysis • array section • code layout Optimization (fully integrated) • inlining • cloning • dead function and variable elimination • constant propagation CMPUT 680 - Compiler Design and Optimization

8. IPA Design Features • User transparent • Provide info (e.g. alias analysis, procedure properties) smoothly to: • loop nest optimizer • main optimizer • code generator CMPUT 680 - Compiler Design and Optimization

9. Loop Nest Optimizer/Parallelizer • All languages (including OpenMP) • Loop level dependence analysis • Uniprocessor loop level transformations • Automatic parallelization CMPUT 680 - Compiler Design and Optimization

10. Loop Level Transformations • Based on unified cost model • Heuristics integrated with software pipelining • Loop Fission • Loop Fusion • Loop Unroll and jam • Loop interchange • Loop Peeling • Loop Tiling • Vector data prefetching CMPUT 680 - Compiler Design and Optimization

11. Parallelization • Automatic Array privatization Doacross parallelization Array section analysis • Directive based OpenMP Integrated with automatic methods CMPUT 680 - Compiler Design and Optimization

12. Global Optimization Phase • Use only SSA as program representation • SSA is unifying technology • Implements all traditional global optimizations • Every optimization preserves SSA form • Can reapply each optimization on as-needed basis CMPUT 680 - Compiler Design and Optimization

13. Pro64 Extensions to SSA • Representing aliases and indirect memory operations • Integrated partial redundancy elimination (SSA PRE) • Support for speculative code motion • Register promotion via load and store placement CMPUT 680 - Compiler Design and Optimization

14. Feedback Used throughout the compiler • Instrumentation can be added at any stage • Explicit instrumentation data incorporated where inserted • Instrumentation data maintained and checked for consistency through program transformations. CMPUT 680 - Compiler Design and Optimization

15. Design for Debugability (DFD) and Testability (DFT) • DFD and DFT build-in from start • Can build with extra validity checks • Simple option specification used to: • Substitute components known to be good • Enable/disable full components or specific optimizations • Invoke alternative heuristics • Trace individual phases CMPUT 680 - Compiler Design and Optimization