Embedded hardware and software self testing methodologies for processor cores
This presentation is the property of its rightful owner.
Sponsored Links
1 / 19

Embedded Hardware and Software Self-Testing Methodologies for Processor Cores PowerPoint PPT Presentation


  • 72 Views
  • Uploaded on
  • Presentation posted in: General

Embedded Hardware and Software Self-Testing Methodologies for Processor Cores. Li Chen, Sujit Dey, Pablo Sanchez, Krishna Sekar, and Ying Chen Design Automation Conference, 2000 Page(s): 625~630 Presented by Kao, Chung-Fu. What’s the Problems ? .

Download Presentation

Embedded Hardware and Software Self-Testing Methodologies for Processor Cores

An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -

Presentation Transcript


Embedded hardware and software self testing methodologies for processor cores

Embedded Hardware and Software Self-Testing Methodologies for Processor Cores

Li Chen, Sujit Dey, Pablo Sanchez, Krishna Sekar, and Ying Chen

Design Automation Conference, 2000

Page(s): 625~630

Presented by

Kao, Chung-Fu


What s the problems

What’s the Problems ?

  • Current external testers vs. GHz processors.

    • Test speed, equipment cost ($20 million)

  • Does hardware BIST good enough ?

  • Why not Software-Based Self-Testing.

    • Low cost, high-quality self-test methodology


Outline

Outline

  • Introduction

  • Two case: PARWAN and PicoJava-II processor cores

    • Proof that hardware BIST still has many limitations

  • Demonstrate that software-based self-testing methodology is a better approach

  • Experiment and conclusion


Introduction

Introduction

  • Generate the required test patterns on-chip

    • At-speed testing, reduce the cost

  • Built-In Self-Test (BIST)

    • Use for memory logic due to regular structure

  • How to test non-memory parts ?

  • Software-based self-testing


Preliminary

Preliminary

  • The commercial logic BIST tool: LBIST

    • Applying BIST to two processor cores

The design-under-test often has to be modified extensively to be random pattern testable


Case study i parwan

Case Study I: PARWAN

  • We should modify the design in order to make the application of LBIST effective.

  • Splitting all bi-directional pins into separate I/O pins

  • Replacing all tri-state buffers with selectors

  • Inserting test points to improve the testability of the circuit


Experiment

LFSR, MISR, boundary scan

Use test points

Experiment

* On the modified circuit

** On the modified circuit with test points


Case study ii picojava ii

Case Study II: PicoJava-II


Software based self testing

Software-Based Self-Testing

  • Uses a software tester embedded in the processor memory

  • For test generation and test application

  • Advantages

    • Programmability;

    • Flexibility;

    • Generates desirable random test sets on-chip

    • No need of scan chains and boundary scan


The software based self testing methodology

The Software-Based Self-Testing Methodology

  • The self-testing scheme includes two steps

    • Test preparation step

    • Self-testing step


Step 1 component test preparation

Step 1: Component Test Preparation

  • The test need of the component by aself-test signature

    • The seed (S)

    • The configuration (C)

    • The number of test patterns to be generated (N)

  • Instruction-based testing


Instruction imposed constraints

in_flag

(vcnz)

data_in

8

4

8

4

SHU

asl

asr

data_out

out_flag

Hardware paths involved in testing the SHU

Instruction-Imposed Constraints

  • Spatial constraints

  • Temporal constraints

  • Ex:

  • asl and asr can not be both 1,

  • z and n must be consistent with data_in,

  • v = xor (c, sign_bit (data_in) )


Constraint modeling

Constraint Modeling

  • Spatial constrain

    • Random patterns used on independent inputs

  • Temporal constrain

    • As figure shown


Step 2 on chip self test

Step 2: On-Chip Self-Test

  • Uses an embedded software tester for the on-chip generation


Test generation program

external XOR gate

polynomial = 101 (1+x2)

Seed (011)

Test Generation Program

  • Using pseudo random number generator

  • The S/W program emulating a H/W LFSR (Linear Feedback Shift Register)

Q = S

DoN times

begin

AC = Bitwise-and (C, Q);

New_bit = Parity (AC);

Q = New_bit : (Q >> 1);

end

Hardware Implementation


Test application program

Test Application Program

  • Outputs observation

    • Data outputs

    • Status outputs

0 lda addr (y)// load AC

1 add addr (x)

2 sta data_out// store AC

3 lda 11111111

4 brav ifv// branch if overflow

5 and 11110111

6 label ifv brac ifc// branch if carry

7 and 11111011

8 label ifc braz ifz// branch if zero

9 and 11111101

10 label ifz bran ifn// branch if negative

11 and 11111110

12 label ifn sta flag_out


Experimental results

Prepares a VHDL test bench containing the initialized instruction memory and data memory

Run the test bench, and captures the input signals to the processor. These are the test vectors to be applied during fault simulation

Experimental Results

  • Test evaluation framework


Experimental results cont d

Experimental Results (cont’d)

* Test pattern generation program


Conclusion

Conclusion

  • Demonstrated some of the disadvantages associated with H/W-based BIST tech.

  • We hope that no need to change design when insert the test mechanism.

  • Software-based self-testing tech. had proposed

    • No hardware overhead

    • Save money


  • Login