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I/O Methods

I/O Methods. I/O – Transfer of data between memory of the system and the I/O device Most devices operate asynchronously from the CPU Most methods involve CPU in performing actual transfer Direct I/O Polled/Programmed I/O Interrupt Driven I/O Direct Memory Access. Direct I/O.

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I/O Methods

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  1. I/O Methods • I/O – Transfer of data between memory of the system and the I/O device • Most devices operate asynchronously from the CPU • Most methods involve CPU in performing actual transfer • Direct I/O • Polled/Programmed I/O • Interrupt Driven I/O • Direct Memory Access

  2. Direct I/O • Only suitable for some I/O devices • Simple devices – LEDs, simple switches etc. • Device always ready to transfer data • No status checking required Example: Simple Port I/O for Microchip PIC PORTB = PORTB | 0x40; x = PORTA; PORTBBits.3 = 1;

  3. Polled/Programmed I/O • Device indicates readiness to transfer data. • Typically the device has a status flag that can be interrogated by the CPU • CPU, under program control, reads (polls) the status waiting for the device to indicate readiness to transfer data • Wastes CPU cycles (busy-waiting) • Simple to understand and implement. • CPU in control and performs the actual transfer

  4. Interrupt Driven I/O • Device has an output signal that is connected to a special signal of the CPU • The device asserts the signal when it is ready to transfer data (Interrupt request) • The CPU may ignore the request – the interrupt is said to be masked) • Some CPUs have a special interrupt that is non-maskable. For very important interrupts such as alarms, power failure etc.

  5. Interrupt Driven I/O • Interrupt processing is unique to each CPU. Typical features • Enabled interrupts checked after each machine instruction. • Interrupt requests are usually prioritised • Most CPUs use an interrupt vectoring system • Each possible interrupt source is allocated a particular vector number/address • The CPU vectors to the address in the table and continues executing instructions. • The CPU returns to executing the interrupted program on encountering the special machine instruction Return from Interrupt

  6. Typical Interrupt Processing Interrupt processing VECTOR TABLE # Address Instruction 0 0000H 1 0004H 2 etc 35 008CH JUMP ISR 36 0090H normal program execution ISR: store regs. --------- ---------- ---------- ---------- ---------- restore regs. Return from Interrupt ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- Interrupt request Return to interrupted program NB Interrupting device allocated to vector # 35

  7. Interrupt Processing (contd.) • Program counter(PC) is automatically pushed on the stack – possibly other regs. • The vector address is generated by the interrupt hardware. • The interrupt service routine (ISR) should preserve any registers that are used in the ISR. • A special return from interrupt instruction should restore the PC and normal program execution should resume. • An ISR may be interrupt by a higher priority request. • The interrupt request is usually cleared by the hardware when it generates the vector.

  8. Interrupt Processing (contd.) • Potential problems • Re-entrancy of functions • Sharing of variables – mutual exclusion • Solutions • Keep interrupt processing code to a minimum • Do not call other functions in the ISR • For shared variables use a data type that is accessed with an indivisible instruction e.g. single bit • Disable interrupts during shared variable access.

  9. Direct Memory Access (DMA) • Requires a DMA controller • Data transferred without CPU being involved • CPU programs the DMA controller • set transfer direction – input or output • Start address in memory • Number of bytes to transfer • Can copy memory to memory • DMA controller performs the transfer between the memory and the I/O device • DMA controller interrupts CPU on completion

  10. DMA (Contd.) • DMA signals – bus request, bus grant • Operation • DMA request asserted • CPU generates DMA bus grant • CPU bus accesses suspended (CPU tri-stated) • DMA controller performs a memory transfer • DMA request negated • Two modes • Cycle stealing – DMA and CPU interleave accesses • Burst mode

  11. Summary • Direct I/O – limited usage • Polled/Programmed I/O • CPU initiates transfer request and data transferred by CPU between memory and I/O device. • Simple but wastes CPU time • May miss input data if data rate is higher than input sampling frequency. • Good for well defined periodic slow devices • Poor for input devices and non-periodic device

  12. Summary (Contd.) • Interrupts • I/O device initiates transfer • CPU via software still performs the data transfer • Good for non-period, asynchronous devices • Every interrupt incurs a time overhead • Very high interrupt rates can overload the CPU • Requires extra programming to set up the interrupt and interrupt service routine. • Can be difficult to test & debug • Examples: Keyboard input.

  13. Summary (Contd.) • DMA • Requires additional hardware • Good for transferring large blocks of data • CPU not involved in transferring data • Good for high data rates • Examples: Hard Disks, Network card

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