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Processor Design. Clocking Methodology Defines when signals can be read and written Going to assume an edge triggered clocking methodology. Control Step. Each control step takes one clock cycle. Source registers output here. Destination registers read values here. Clock cycle.

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Processor Design

  • Clocking Methodology

    • Defines when signals can be read and written

    • Going to assume an edge triggered clocking methodology


Control Step

  • Each control step takes one clock cycle

Source registers output here

Destination registers read values here

Clock cycle

Signals propagate through system


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Datapath Design

Chapter 5 P & H


Introduction

  • Designing an implementation which contains subset of core MIPS instruction set:

    • Memory reference instructions (lw & sw)

    • Arithmetic-logic instructions (add, sub, and, or and slt)

    • Branch and jump instructions (beq, j)


Overview of Implementation

  • Consider execution of an instruction

  • First two steps identical

    • Use PC to fetch an instruction from memory

    • Read 1 or 2 registers as specified in instruction

  • Rest of steps dependent on instruction class

    • Most will use ALU

    • Many write value back to register file


Overview of Implementation

  • Will start with simple single cycle implementation

  • Implementation will comprise datapath plus control


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Instruction Fetch


R-type Instructions

  • All R-type instructions:

    • Read two registers

    • Perform some ALU operation

      • add, sub, slt, and, or, etc.

    • Write the result back to the register file


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Datapath for R-Type Instructions


lw and sw Instructions

  • lw $7, offset($8) or sw $7, offset($8)

  • These instructions

    • Compute the memory address (16 bit signed offset + base register)

    • If sw then value must also be loaded from reg file

    • If lw the value read from memory must be stored to reg file

    • rs contains base, rt contains src/dst register

  • Need to sign-extend offset to 32-bit value

  • OP, RS, RT are same format/place as w/ R-type

    • Simplicity favours regularity


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Datapath for lw and sw


beq Instruction

  • beq $7, $8, offset

  • if ($7 == $8) then pc <= pc + 4 + (offset << 2)else pc <= pc + 4


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beq datapath


Simple Implementation Scheme

  • All instructions execute in single clock cycle:

    • No data path resource used more than once per clock cycle

    • Components of different instruction classes may be shared if no conflicts occur

      • May require multiple connections to same input

      • Multiplexer used to select appropriate input


Combining datapath for R-type and memory instructions

  • Datapaths very similar

  • Two main differences

    • Second input to ALU is a register (for R-type) or sign-extended lower half of instruction (lw and sw)

    • Value stored in dest register comes from ALU (R-type) or memory (lw)


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Combined Datapath


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Adding Datapath for instruction fetch


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Add in beq components


For R-Type instructions need to perform operation dependent of function field

For load instructions use ALU to compute memory address by addition

For branch instructions ALU used for subtraction

ALU Control


Truth Table for ALU control

  • Note multiple levels of control

    • Main control unit generates ALUOp

    • ALU control generates operation


Main Control Unit Design

  • Opcode fields always bits 31 – 26 (Op[5-0])

  • Two regs to be read are always rs and rt

  • Base reg for loads and stores always rs

  • 16 bit offset always bits 15 – 0

  • Destination register is in one of two places

    • r-type instructions RD

    • lw it is RT


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d

Z

e

r

o

r

e

g

i

s

t

e

r

2

I

n

s

t

r

u

c

t

i

o

n

0

R

e

g

i

s

t

e

r

s

A

L

U

R

e

a

d

A

L

U

[

3

1

0

]

0

R

e

a

d

W

r

i

t

e

A

d

d

r

e

s

s

M

d

a

t

a

2

r

e

s

u

l

t

1

d

a

t

a

I

n

s

t

r

u

c

t

i

o

n

r

e

g

i

s

t

e

r

M

u

M

u

m

e

m

o

r

y

x

u

I

n

s

t

r

u

c

t

i

o

n

[

1

5

1

1

]

W

r

i

t

e

x

D

a

t

a

1

x

d

a

t

a

1

m

e

m

o

r

y

0

W

r

i

t

e

d

a

t

a

1

6

3

2

I

n

s

t

r

u

c

t

i

o

n

[

1

5

0

]

S

i

g

n

e

x

t

e

n

d

A

L

U

c

o

n

t

r

o

l

I

n

s

t

r

u

c

t

i

o

n

[

5

0

]

Datapath with Control Unit


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