G.Albareda , D.Jimenez and X.Oriols Universitat Autònoma de Barcelona - Spain

1. Can analog and digital applications tolerate the intrinsic noise for aggressively scaled field-effect transistors? • G.Albareda, D.Jimenez and X.Oriols • Universitat Autònoma de Barcelona - Spain • E.mail: Guillem.albareda@uab.cat Lyon, FRANCE June 2-6, 2008

2. Outline I.- Introduction: 3D, 2D and 1D ballistic nanoscale FETs I.1.- Intrinsic noise in ballistic nanoscaleFETs I.2.- Analytical Signal-to-noise ratio (S/N) I.3.- Analytical Bit-error ratio (BER) II.- Monte Carlo simulation of 3D, 2D and 1D FETs II.1.- Simulator description II.2.- Numerical results III.- Conclusions

3. I.1.- Intrinsic noise in ballistic 3D, 2D and 1D FETs The size of the transistors shrinks for faster and smaller microchips Ly Lx Lz 1,2,3,4 gates to improve gate control (Lx>Ly,Lz) 1,2,3,4 gates to improve gate control (Lx>Ly,Lz) When Ly and Lz become comparable to the electron de Broglie wavelength, the wave-nature of the electron is manifested. Ly Lz 3D Bulk FET Ly Lz 2D Quantum Well FET Ly Lz 1D Quantum-Wire FET

4. I.1.- Intrinsic noise in ballistic 3D, 2D and 1D FETs Study the noise performance of these aggressively scaled FET in analog and digital circuit applications OUR GOAL I(t) We only consider the “intrinsic” sources of noise due to electron-electron interactions (intrinsic field-effect) .- Exclusion (Pauli) interaction in the contacts .- The Coulomb interaction in the active region We consider ballistic (“ideal”) FETs: No phonon scattering No surface roughness No impurity scattering

5. RL I.2.- Signal to noise ratio (S/N) Analog FET amplifier 3D  30 x 10 x 8 nm3 G  0

6. RL RL I.2.- Signal to noise ratio (S/N) IDS(t) Analog FET amplifier D IDS(t) NS IDS(t) G S IDS(t) In the saturation region G0: Using the superposition principle: For

7. I.2.- Signal to noise ratio (S/N) Ly The role of electron confinement on the average and noise current Lx Lz S/N3D > S/N1D S S D D

8. Bit error ratio (BER): Vth Vo Vi 1 0 D C NS IDS(t) IDS(t) G S I.3.- Bit error ratio (BER) in digital applications Digital FET inverter: VCC VCC OFF ON noisless P P ‘0’ ‘1’ ‘1’ ON OFF N N N N noisy IDS(t)  0

9. Bit error ratio (BER): Vth Vo VCC VCC OFF ON noisless P P ‘0’ ‘1’ Vi ‘1’ A/2 1 0 ON OFF N N N N noisy D C NS IDS(t) IDS(t) G S I.3.- Bit error ratio (BER) in digital applications Thermal noise: Voltage fluctuations: IDC Noise Power: C3D > C1D  BER3D < BER1D [ref] L.B.Kish, Physics Letters A 305 (2002) 144-149.

10. Outline I.- Introduction: 3D, 2D and 1D nanoscale FETs II.- Monte Carlo simulation of 3D, 2D and 1D FETs II.1.- Simulator description: II.1.1.- Confined particles in 1D FETs II.1.2.- Exact 3D Coulomb interaction II.1.3.- Electron injection model with “Pauli” correlations and charge neutrality II.2.- Numerical results: II.2.1.- Average current II.2.2.- Signal to noise ratio II.2.3.- Bit error ratio III.- Conclusions

11. II.1.1.- Confined particles in 1D FETs Silicon (100) channel orientation Lx=15 nm Ly=5 nm Lz=2 nm 1-D y Ly No electron confinement Lx Lz z Quantum potential for the x system Guess: E y x This guess is quite accurate when there is only one relevant quantized energy [ref] X.Oriols, Physical Review Letters, 98, 066803 (2007)

12. ERROR Long-range + Short-range Long-range # e- per cell > 1 mean-field (1 Poisson Eq.) # e- per cell = 0 or 1 DX 1nm-5nm II.1.2.- Exact 3D Coulomb interaction 3D Coulomb interaction beyond the mean-field approximation • Exact term • NOT SEPARABLE • Mean-field • SEPARABLE Long-range Long-range + Short-range exact-field (N Poisson Eqs.) [ref] G.Albareda et al, J. Comp. Electr. (2008)

13. II.1.3.- Electron Injection model with “Pauli” correlation and charge neutrality Pauli correlation Time-dependent version of Landauer-Buttiker boundary conditions Temperature ; T>0 I(t) e 0 e e Binomial injection process t [ref] X.Oriols et al. Solid State Electronics, 51, 306 (2007) [ref] T.Gonzalez, Semicond. Sci. Technol. 14, L37 (1999)

14. II.1.3.- Electron Injection model with “Pauli” correlation and charge neutrality Charge neutrality Our injection model, coupled to the boundary conditions of the Poisson equation, does also assures charge neutrality at the contacts Continuity equation For a good conductor  Local Gauss equation t =/ Practical Monte Carlo implementation At each time step: [ref] H.Lopez, G.Albareda et al., J. Comp. Electr. (2008)

15. II.2.1.- Average current Average current No scaling rule: SiO2 oxide thickness: tox=2 nm Contact doping: 2·1019cm-3 Vgate Vdrain ‘0’0V ‘1’0.5V Vgate 3D  30 x 10 x 8 nm3 1D  15 x 5 x 2 nm3 =0.35V =0.5V

16. II.2.2.- Signal-to-noise ratio S/N comparison 3D Average current > 1D Average current 3D Fano Factor < 1D Fano Factor Amplifying configuration (saturation region) Vdrain=0.5 V Vgate Vgate

17. II.2.3.- Bit-error-degradation BER error probability Efd Vgate=0.5 V 1 1 0 ECd Efs 5ns simulations (time step=2·10-16) ECs Vgate=0.5 V

18. II.2.3.- Bit-error-degradation BER error probability 3D 1D 5THz 5THz 1THz 1THz C=1·10-18F C=5·10-18F 500GHz 50GHz 50GHz 500GHz According to our analitycal estimation, smaller FETs (capacitors) are noisier. Vgate=0.5 V Our 3D FETs can hold frequencies up to 500GHz Our 1D FETs can’t hold frequencies of 500GHz Vgate=0.5 V

19. III.- Conclusions We have developed an accurate Monte Carlo simulator for 3D, 2D and 1D nanoscale FET. For analog applications, smaller devices produce a minor average current and a larger Fano factor, leading to a signal-to-noise (S/N) degradation. For digital applications, smaller devices are more sensible to electrostatics (i.e. smaller capacitance), and provide a degradation of the Bit Error Ratio (BER). In summary, Smaller FETs are noiser for either analog or digital applications. Merci beaucoup