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Reconfigurable ECO Cells for Timing Closure and IR Drop Minimization

Reconfigurable ECO Cells for Timing Closure and IR Drop Minimization. TingTing Hwang Tsing Hua University, Hsin-Chu. Outline. Introduction Engineering Change Order (ECO) Voltage drop (IR-DROP) New design style Cell level Chip level New design style for ECO flow RECON ECO algorithm

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Reconfigurable ECO Cells for Timing Closure and IR Drop Minimization

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  1. Reconfigurable ECO Cells for Timing Closure and IR Drop Minimization TingTing HwangTsing Hua University, Hsin-Chu

  2. Outline • Introduction • Engineering Change Order (ECO) • Voltage drop (IR-DROP) • New design style • Cell level • Chip level • New design style for ECO flow • RECON ECO algorithm • Experimental results • Conclusions

  3. Outline • Introduction • Engineering Change Order (ECO) • Voltage drop (IR-DROP) • New design style • Cell level • Chip level • New design style for ECO flow • RECON ECO algorithm • Experimental results • Conclusions

  4. Engineering Change Order (ECO) • Incremental change of a design • To fix bugs • To meet timing constraint • To meet small change of functionality • Small modification instead of redesign a circuit • To save the reiteration of design flow • To reduce the cost of mask-making

  5. Spare Cells in ECO • Spare cells (NOT, NOR, NAND) are placed evenly in layout at physical design • Spare cells are then used for modification in ECO flow

  6. Outline • Introduction • Engineering Change Order (ECO) • Voltage drop (IR-DROP) • New design style • Cell level • Chip level • New design style for ECO flow • RECON ECO algorithm • Experimental results • Conclusions

  7. Voltage Drop • Power source fluctuations become serious • High performance • Lower supply voltage • VDD/GND variations • Chip speed • Noise margin • Adding decoupling capacitance (decap) is an effective way to reduce power noise [Sachin, TCAD 2003]

  8. New ECO Design Flow • A new reconfigurable (RECON) cell structure • Served as spare cell and decoupling capacitor • Leakage reduction • Free selecting of function type • Demonstration of RECON cell by an ECO algorithm for timing closure and IR drop minimization

  9. Outline • Introduction • Engineering Change Order (ECO) • Voltage drop (IR-DROP) • New design style • Cell level • Chip level • New design style for ECO flow • RECON ECO algorithm • Experimental results • Conclusions

  10. Two PMOS transistor with same transistor width Two NMOS transistor with same transistor width Eight CONTACTs VDD and GND implemented by layer of metal-1 RECON Base Cell

  11. VDD VDD GND GND DECAP Cell • Configured from RECON base cell • Use Metal-1 connection Schematic of cell

  12. Functional Cell (a) Inverter (b) 2-Input NAND (c) 2-Input NOR • Configured from RECON base cell

  13. Comparisons Between RECON Cells and Standard Cells • Setup of experiment • Cell layouts created with TSMC 0.13um process • SPICE net-lists extracted by RC-extractor • Delay, leakage, internal power and input pin capacitance by SPICE simulation

  14. As Decoupling Cells • Less flexibility of layout • 16%-39% capacitance • 9%-34% leakage

  15. As Functional Cells

  16. Outline • Introduction • Engineering Change Order (ECO) • Voltage drop (IR-DROP) • New design style • Cell level • Chip level • New design style for ECO flow • RECON ECO algorithm • Experimental results • Conclusions

  17. Model of Power Supply Analysis • Cycle-based time frame

  18. Model of Power Supply Analysis (cont.) • Metal layer of VDD and GND modeled as a power-grid resistance • Standard cells modeled as time-varying current source • RECON DECAP cells modeled as capacitors connected between VDD and GND

  19. Supply voltage variation can be derived as following Clock cycle is divided into many time slots Switching gate are derived from static timing analysis Maximum current consumption are calculated in each time slot. Model of Power Supply Analysis (cont.)

  20. IR Drop Analysis of Whole Chip

  21. Leakage Analysis of Whole Chip

  22. Outline • Introduction • Engineering Change Order (ECO) • Voltage Drop (IR-DROP) • New design style • Cell level • Chip level • New design style for ECO flow • RECON ECO algorithm • Experimental result • Conclusion

  23. Differences Between RECON and Traditional ECO Flows • RECON DECAP instead of spare cells are pre-placed • RECON DECAP cells are reconfigured to RECON functional cells when RECON ECO flow is performed • Unselected RECON DECAP cells are kept as decoupling capacitors

  24. Problem Formulation • An ECO path is a path that violates the timing constraint • Given a set of placed gate level net-list, ECO paths and timing constraint, perform gate sizing or buffer insertion on ECO paths • Timing constraint is met • IR drop is minimized

  25. RECON ECO Algorithm Input: a set of ECO paths to be optimized For each ECO path Find the critical gates in ECO paths and put in ECO_gate_list While (timing is not satisfy) Choose the gate from ECO_gate_list with most output loading Perform gate sizing or buffer insertion List_A = search_region(gate_sizing) List_B = search_region(buffer_insertion) For all configurable cell Rg in List_A or List_B If IRdrop(Rg) > threshold Remove Rg in List_A or List_B Candidate_list = List_A + List_B Compute path delay gain for all Rg in Candidate_list Select the best Rg corresponding to the best delay gain Update the ECO path delay End while

  26. Search Region for Gate Sizing D1 D2 D3 D5 D6 D4 Search_region(G4) = Bounding_Box(G3 U G4 U G5 U G6)

  27. Search Region for Buffer Insertion D1 D2 D3 D5 D6 D4 Search_region(G4) = Bounding_Box(G4 U G5 U G6)

  28. Outline • Introduction • Engineering Change Order (ECO) • Voltage drop (IR-DROP) • New design style • Cell level • Chip level • New design style for ECO flow • RECON ECO algorithm • Experimental results • Conclusions

  29. Experimental Setup • ITC99 benchmarks • Benchmarks synthesized to gate-level net-list using TSMC 0.13um process • Standard cells and RECON DECAP cells placed by SOCEncounter • 20% area used to place RECON DECAP cells

  30. Experimental Flow

  31. Statistics of Benchmarking Circuits • Timing constraint is set to 90% of critical path delay in the original circuit

  32. Leakage Comparisons Before ECO

  33. Performance Comparisons Before ECO • Trad: traditional spare cells • RECON: RECON decap cells

  34. Performance Comparisons After ECO • Trad: traditional spare cells • RECON: RECON decap cells

  35. Number of Unsolved Paths After ECO • Trad: traditional spare cells • RECON: RECON decap cell

  36. Conclusions • A new cell structure • Decoupling capacitor cell • ECO spare cell • A reconfigurable ECO flow • 20% IR drop reduction • 44% leakage reduction

  37. Thank you

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