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Joint Research Project for the EU FP 6/I3 HP

Development of Low-mass, Radiation-hard, Fast Silicon Pixel Detectors based on Monolithic CMOS Technology. HI-MAPS. Joint Research Project for the EU FP 6/I3 HP. What we can provide!. What we apply for!. Budget, first draft of application. Proposal of JRP on Solid State Detectors.

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Joint Research Project for the EU FP 6/I3 HP

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  1. Development of Low-mass, Radiation-hard, Fast Silicon Pixel Detectors based on Monolithic CMOS Technology HI-MAPS Joint Research Project for the EU FP 6/I3 HP

  2. What we can provide! What we apply for! Budget, first draft of application

  3. Proposal of JRP on Solid State Detectors • Silicon detectors (G. Stefanini/CERN) • now including amorphous hydrogenated silicon (a-Si:H) (P. Jarron/CERN) • Monolithic Si pixel detector (J. Stroth/GSI) • Diamond detectors (E. Berdermann/GSI) Joint Research Project for the EU FP 6/I3 HP

  4. Rationale of the Merging • Common objectives in the development of detectors and associated electronics • Low material budget, low power, high integration, high speed, radiation hardness • Common challenging problems • Low mass mechanical supports and cooling system, interconnects (E/O), reliability • Detector technologies with different levels of maturity • Hybrid Si pixels state of the art • Amorphous Si detectors novel, proof of principle (a-Si:H layer on ASIC) • Monolithic Si pixels early prototyping • Diamond new: single crystals (high CCE), potential for very high speed and radiation hardness • Joint effort to acquire and share new knowledge, methods, access to facilities, expertise • Compare test results and performance with established bench marks • Contribute to innovation in specific technologies, improve the definition of requirements and performance assessment, facilitate the decision process

  5. Sandwich of a sensor substrate bump bonded to the readout chip High Resolution High rate Radiation hard Sparse data scan but Material budget (x/X0  1 %) Complex fabrication Based on CMOS light sensors. With integrated signal processing on the same substrate. Highest Resolution Minimal pixel size Cheap Low mass but Moderately radiation tolerant Slow Maybe a-SI:H !!! Hybrid vs. Monolithic HPS MAPS

  6. amorphous-Si:H Detectors Experimental high rate Reactor at IMT Neuchatel T deposition in plasma 220 C First experimental pixel a-Si:H deposited on a fast readout ASIC a P.I.N is formed: P and N ultra thin Collection in the thick I layer slide by courtesy of G. Stefanini, CERN

  7. First results with a-Si:H detector demonstrator (P. Jarron - unpublished) Excitation pulse 2ns width from laser l = 660nm • Input charge ≈ 2 fC ≈ 12,000 electrons • a-Si:H layer thickness 13mm, bias voltage 70V (depletion) Single shot 1fC signal Rise time 6ns FWHM: 25ns ENC 250 rms electron Signals measured on 13 pixel 100m x 100m Charge collection 70% in 40 ns slide by courtesy of G. Stefanini, CERN

  8. First results with a-Si:H detector demonstrator (II) • Proof of principle established • detector with a-Si:H layer on top of IC • rise time 6 ns, signal width 25ns • slow signal tail limited to 200ns (transport of holes and electrons in deep states) • First lab performance test • very low bulk leakage current <1nA/cm2 • edge leakage current 500nA caused by imperfect lift off • stability: tested over several days operation with bias on • good uniformity pixel to pixel

  9. Objectives for a-Si:H Detector Development • Optimize a-Si:H material quality for hadron detector • Optimize high deposition PECVD rate reactor • Minimize unpassivated defects, minimize internal mechanical stress for large area detector • Optimize process for very high field • Characterise charge transport • Radiation hardness: expected to exceed 1015 p/cm2 thanks to spontaneous annealing of defects with hydrogen (≈ 15% of mass in a-Si:H) - to be tested • Develop lithography technology for ‘above IC’’ • Adapt patterning and masking technique, develop metallurgy of contact • Develop readout ASIC to detect charge packets of 100 to 1000 e- • Optimized layout technique for ‘above IC’ technology • Ultra low power CMOS circuit, readout architecture adapted to high density pixel • Manufacture demonstrators and prototypes • Large area samples of a-Si:H layer on ultra thin substrate • Linear array of a-Si:H pixel detector 25 micron pitch • 2D a-Si:H pixel detector 25 micron pitch

  10. Objective • Verify the applicability of MAPS for high rate, high-multiplicity nuclear experiments • Increase readout speed • Data driven, 107 interactions/s • on-chip sparsification/buffering • Improve radiation tolerance • Fluence up to 1016 n/cm2 • Reduce material budget • Detector, support, cooling (low power designs), data transport

  11. L.N.S. Network Partners • Industrial companies • Centers of Excellence Heavy Ion & HadronPhysics Monolithic Active Pixels

  12. M. Winter et al., IReS MIMOSA • Prototype chips developed at IReS in collaboration with LEPSI • no performance degrading up to 1012 n/cm2 • MIMOSA 6 first chip with sparsification on the chip available end of 2002 (now)

  13. M. Winter et al., IReS Facts after 1st round of simulations Beam pipe of 1 cm Ø Fluence above 1016 Pixel Strip

  14. CBM Silicon Working Group

  15. Next steps to take • 2nd generation of simulations • refine geometry • define acceptable thickness • Define working packages • Prepare 1st CBM-Silicon working group meeting

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