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FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimisation in Lookup-Table Based FPGA Designs. Presented by Qiwei Jin. 10/09/2014. Overview. The paper and the authors. Some background information. The algorithm in detail. Results and Conclusion. Questions for discussion.

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FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimisation in Lookup-Table Based FPGA Designs

Presented by Qiwei Jin

10/09/2014


Overview
Overview Optimisation in Lookup-Table Based FPGA Designs

  • The paper and the authors.

  • Some background information.

  • The algorithm in detail.

  • Results and Conclusion.

  • Questions for discussion.


About the paper
About the Paper Optimisation in Lookup-Table Based FPGA Designs

  • Originally published in 1992, won IEEE Circuit & Systems Society best paper award in 1994.

  • 238 citations in total, 33 self.

  • The firstalgorithm to solve a conventionally NP-hard depth minimisation problem in polynomial time.

  • The algorithm is a key component in most commercial FPGA compilers.

  • FlowMap-r and other more sophisticated algorithms published by the authors at the same year or later for both depth and area minimisation.


Jason cong
Jason Cong Optimisation in Lookup-Table Based FPGA Designs

  • Chairman of Computer Science Department, UCLA.

  • Was Assistant Professor in 1994 when this paper was published.

  • Got Promoted to Associate Professor in the same year.

  • His company Aplus was acquired by Magma in 2004 for "$13 million in stock, cash and incentives“.

Picture borrowed from Jason Cong’s homepage


Yuzheng ding
Yuzheng Ding Optimisation in Lookup-Table Based FPGA Designs

  • Very low profile person, no picture, no home page, not even on FaceBook.

  • RA in UCLA for PhD when this paper was published.

  • May have left university for work (Mentor Graphics) after graduation.

  • Still working actively with Jason Cong, latest paper published in year 2008.


Background
Background Optimisation in Lookup-Table Based FPGA Designs

  • FPGA (Field-Programmable Gate Array): Programmable hardware.

Xilinx Virtex 5 FPGA


Background cont
Background Cont. Optimisation in Lookup-Table Based FPGA Designs

For more information, go to Wayne Luk’s Custom Computing Course


Background cont1
Background Cont. Optimisation in Lookup-Table Based FPGA Designs

  • FPGAs are essentially a bunch of wires and LUTs (Look-Up Tables) that can be configured to emulate the behaviour of a digital circuit.

  • FPGAs can be configured by Hardware Description Language (HDL, such as VHDL).

  • Based on the HDL, a netlist can be generated automatically by some algorithm (FlowMap!).


Background cont2
Background Cont. Optimisation in Lookup-Table Based FPGA Designs

=

4-Input 1-Output LUT (16 entries in total)


Background cont3
Background Cont. Optimisation in Lookup-Table Based FPGA Designs

  • Mappings from ASIC to FPGAs are not necessary one to one.

  • The question is how to achieve the optimal condition?

=


Background cont4
Background Cont. Optimisation in Lookup-Table Based FPGA Designs

  • Trade-offs:

    • Area (number of LUTs used)

    • Depth (delay of the circuit)

  • FlowMap focuses on depth optimisation

depth


Depth minimisation example
Depth Minimisation Example Optimisation in Lookup-Table Based FPGA Designs


The key idea of depth minimisation
The Key Idea of Depth Minimisation Optimisation in Lookup-Table Based FPGA Designs

  • Try to pack as many gates in different levels into a LUT as possible.

  • Number of LUT used (Area) is not the primary concern.

  • The problem is equivalent to generating optimal code for expressions containing common subexpressions, hence NP-Hard.*

  • Conventional method will decompose the Boolean network into a forest of trees before processing.

  • FlowMap can find an optimal mapping directly from a Boolean network within polynomial time.

    Let’s see how.

* A. Aho, S. C. Johnson, “Optimal Code Generation for Expression Trees”, 23, 3, 488-501 (1976).


Preliminaries
Preliminaries Optimisation in Lookup-Table Based FPGA Designs

  • Input(T)

  • Cut (X, X)

  • Node Cut Size

  • Edge Capacity

  • Edge Cut Size

  • Whether a cut is K-feasible

  • Height of a Cut


The flowmap algorithm
The FlowMap Algorithm Optimisation in Lookup-Table Based FPGA Designs

  • 2 Phases

    • Node Labeling: define the optimal depth of the LUT mapping solution for Nt.

    • LUT Mapping: generate the LUT network based on the labeling in the first phase.


Phase 1 node labelling
Phase 1: Node Labelling Optimisation in Lookup-Table Based FPGA Designs


Phase 1 node labelling cont
Phase 1: Node Labelling Cont. Optimisation in Lookup-Table Based FPGA Designs


Phase 2 lut mapping
Phase 2: LUT Mapping Optimisation in Lookup-Table Based FPGA Designs


Phase 2 lut mapping cont
Phase 2: LUT Mapping Cont. Optimisation in Lookup-Table Based FPGA Designs


The flowmap pseudocode
The FlowMap Pseudocode Optimisation in Lookup-Table Based FPGA Designs


Enhancements
Enhancements Optimisation in Lookup-Table Based FPGA Designs

  • Maximising Cut Volume During Mapping

  • Postprocessing (flow-pack) Operations to reduce number of K-LUTs


Results
Results Optimisation in Lookup-Table Based FPGA Designs


Conclusion
Conclusion Optimisation in Lookup-Table Based FPGA Designs

  • The paper presents the first algorithm to compute a NP-hard problem in polynomial time.

  • Compared to other algorithms FlowMap is about to reduce up to 7% of the LUT network and reduce up to 50% of the number of LUTs.


Questions
Questions Optimisation in Lookup-Table Based FPGA Designs

  • It is claimed that a minimum height K-feasible cut can be found in O(Km) time, where K is the number of input of LUT and m is the number of edges of in the network.

  • But it is not clear to me how it is derived.


Questions cont
Questions Cont. Optimisation in Lookup-Table Based FPGA Designs

  • It would be interesting to see the time taken to compute the mapping for the testing cases with FlowMap vs. Other Algorithms.

  • The testing cases are generally small in size, it would be more convincing to see some large size examples.


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