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PRESENTED BY YONGQUAN CHAI VIKRAM MADINENI

VENDING MACHINE CONTROLLER. PRESENTED BY YONGQUAN CHAI VIKRAM MADINENI. CONTENTS. INTRODUCTION TO VENDING MACHINES VENDING MACHINE CONTROLLER DESIGN AND PROGRAMMING CONCLUSION & FUTURE SCOPE. INTRODUCTION TO VENDING MACHINES.

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PRESENTED BY YONGQUAN CHAI VIKRAM MADINENI

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  1. VENDING MACHINE CONTROLLER PRESENTED BY YONGQUAN CHAI VIKRAM MADINENI

  2. CONTENTS • INTRODUCTION TO VENDING MACHINES • VENDING MACHINE CONTROLLER • DESIGN AND PROGRAMMING • CONCLUSION & FUTURE SCOPE

  3. INTRODUCTION TO VENDING MACHINES • The history of Vending Machine (or” automatic retailing “as it is increasingly known) dates back to the time of B.C. • In the early 1880’s first commercial coin operated vending machines were installed in London to dispense the stamps. • The first vending machines in USA were installed in the year 1888 by the Thomas Adams Gum Company and it sold Tutti-Fruiti gum. • Now Vending Machines offer everything stamps , food products, drinks ,cigars etc. and have become a part of our lives.

  4. VENDING MACHINE CONTROLLER • Most of the vending machines being used are microcontroller based and as the number of functions and products increase, the complexity of controller is also increased. • We feel VHDL programis less complex and cost effective when implemented small scale vending machine. • We have developed VHDL code for a vending machine, which will be targeting small Offices , Motels etc. where the number of products required is limited.

  5. Money Vending Machine Deliver Door Return all Money Selection Money Return Clock • Money can be inserted in the combination of nickel, dime, quarter or dollar. • Three products are available – 1. Pepsi 2. Cookies 3. Chips • Selection is done at the input Block Diagram FIGURE 1

  6. START Insert Money – Nickel, Dime , Quarter or Dollar Select the Prodcut Pepsi Chips Cookies Check Sum Check Sum Check Sum >65c Return All Money <60c Change Available? >50c No Yes Release Changes =60c =65c =50c Release Pepsi Release Cookies Release Chips <65c <50c >60c FLOW CHART

  7. State Assignment • S0: Waiting for money or other instruction • S1: Custom selection (10: Cookies, 01: Pepsi, 11: Chips) • S2: Total money condition 1 (buying Pepsi) • S3: Total money condition 2 (buying Cookies) • S4: Total money condition 3 (buying Chips) • S5: Deliver Pepsi • S6: Availability of changes • S7: Return Change • S8: Return all money • S9: Deliver Cookies • S10:Deliver Chips

  8. Mny’,Rtn’ Sum<50 S0 S2 Sum=50 Mny, Rtn’ Sel:01 Sum>50 Sum<60 S1 S6 S5 Mny’, Rtn Sel:10 Sel:11 Sum>65 Sel:01 Change Available S3 Sum>60 S4 S7 Sum=65 Sel:10 Sel:11 Sum<65 Sum=60 S10 S9 S8 FIGURE 2STATE DIAGRAM OF VENDING MACHINE CONTROLLER

  9. State Table Outputs Present State Next State TABLE 1

  10. beginprocess ( clk,S)beginCase S is when 0 =>Pe <='0';Co <='0';Ch <='0';if Sum =0 then Sum <= Sum+Sum1(Mny); end if;if Mny = "000" and Rt ='0' then NS <=0; end if;if Mny /= "000" and Rt='0' then NS <=1; end if;if Mny /= "000" and Rt='1' then NS <=8; end if;when 1 =>if Sel ="01" then NS <=2; end if;if Sel ="10" then NS <=3; end if;if Sel ="11" then NS <=4; end if;when 2 =>Sum <= Sum+Sum1(Mny);if Sum < 10 then NS <=0; end if;if Sum = 10 then NS <=5; end if;if Sum > 10 then NS <=6; end if; BEHAVIOR ARCHITECTURE PROGRAM entity Vend isport ( Mny : in bit_vector (3 downto 1); Sel : inout bit_vector (2 downto 1); Rt,Clk,Ca : in bit; Pe,Co,Ch,Rm,Rc : out bit );end vend;architecture Vend_bhv of vend is signal S,NS : integer :=0;signal Sum : integer:=0;function Sum1 (Mny : in bit_vector(3 downto 1))return integer isvariable Sum2 : integer :=0;begin case Mny is when "001" => Sum2:= Sum2+1; when "010" => Sum2:=Sum2+2; when "011" => Sum2:=Sum2+5; when "100" => Sum2:= Sum2+20; when others => null; end case;return Sum2;end Sum1;

  11. when 8 =>Rm<='1'; NS <=0;when 9 =>Rc <='0';Co <='1' ; Sel <="00"; NS <=0;when 10 =>Rc <='0';Ch <='1' ; Sel <="00";NS <=0;when others =>null;end case;end process;process (clk)beginif clk='1' thenS <= NS;end if;end process;end vend_bhv; when 3 =>Sum <= Sum+Sum1(Mny);if Sum < 12 then NS <=0; end if;if Sum = 12 then NS <=9; end if;if Sum > 12 then NS <=6; end if;when 4 =>Sum <= Sum+Sum1(Mny);if Sum < 13 then NS <=0; end if;if Sum = 13 then NS <=10; end if;if Sum > 13 then NS <=6; end if;when 5 =>Rc <='0';Pe <='1' ; Sel <="00";NS <=0; When 6 =>if Ca='0' then NS <=7; end if;if Ca='1' then NS <=8; end if;when 7 =>Rc <='1';if Sel ="01" then NS <=5; end if;if Sel ="10" then NS <=9; end if;if Sel ="11" then NS <=10; end if;

  12. PLOT 1 BEHAVIOR ARCHITECTURE WAVEFORM FOR RELEASE OF CHIPS

  13. PLOT 2 BEHAVIOR ARCHITECTURE WAVEFORM FOR RELEASE OF COOKIES

  14. Money Vending Machine Controller Return All Money Release Pepsi Sum Signals Generation Block Nickel Dime Release Cookies Quarter Sum Dollar Pepsi Release Chips Cookies Return all Money Chips Return Changes Availability of Changes Clock DESIGN PROCEDURE FOR STRUCTURAL ARCHITECTURE FIGURE 3

  15. Vending Machine Controller Money Return all Money Release Pepsi Pepsi Chips Cookies Release Chips Sum<50c Sum=50c Release Cookies Sum>50c Sum<60c Return All Money Sum=60c Sum>60c Return Changes Sum<65c Sum=65c Sum>65c Availability of Changes Clock FIGURE 4

  16. TABLE 2 EXPANDED STATE TABLE FOR DESIGINING THE STRUCTURAL ARCHITECTURE

  17. entity vm is port(Mny,Rtn,Sel01,Sel10,Sel11,S50l,S50e,S50m,S60l,S60e,S60m,S65l, • S65e,S65m,CA,Clk:in bit;Rpp,Rck,Rcp,Rac,Rch: out bit);end vm; • architecture vm_structural of vm is signal S:bit_vector(24 downto 0); signal Q:bit_vector(3 downto 0):="0000"; signal D:bit_vector(3 downto 0); signal N:bit_vector(14 downto 0); signal T:bit_vector(5 downto 0); signal QN:bit_vector(3 downto 0):="1111"; component xor2 port(a,b:in bit;c:out bit); end component; component and4 port(a,b,c,d:in bit;e:out bit); end component; component and5 port(a,b,c,d,e:in bit;f:out bit); end component; component and6 port(a,b,c,d,e,f:in bit;g:out bit); end component; component and7 port(a,b,c,d,e,f,g:in bit;h:out bit); end component; component or5 port(a,b,c,d,e:in bit;f:out bit); end component; component or6 port(a,b,c,d,e,f:in bit;g:out bit); end component; component or7 port(a,b,c,d,e,f,g:in bit;h:out bit); end component; component not2 port(a:in bit;c:out bit); end component; component DFF port(D,clk:in bit;Q:inout bit;QN:inout bit:='1'); end component; beginnot21: not2 port map(Mny,N(0));not22: not2 port map(Rtn,N(1));not23: not2 port map(Sel01,N(2));not24: not2 port map(Sel10,N(3));not25: not2 port map(sel11,N(4));not26: not2 port map(S50l,N(5));not27: not2 port map(S50e,N(6));not28: not2 port map(S50m,N(7));not29: not2 port map(S60l,N(8));not210: not2 port map(S60e,N(9));not211: not2 port map(S60m,N(10));not212: not2 port map(S65l,N(11)); STRUCTURALPROGRAM FOR MAIN BLOCK

  18. not213: not2 port map(S65e,N(12));not214: not2 port map(S65m,N(13));not215: not2 port map(CA,N(14));and61: and6 port map(QN(3),QN(2),QN(1),QN(0),N(0),Rtn,S(0));and71: and7 port map(QN(3),QN(2),Q(1),Q(0),N(8),S60e,N(10),S(1));and72: and7 port map(QN(3),Q(2),QN(1),QN(0),N(11),S65e,N(13),S(2));and51: and5 port map(QN(3),Q(2),Q(1),QN(0),N(14),S(3));xor21: xor2 port map(Sel10,N(4),T(0));and62: and6 port map(QN(3),Q(2),Q(1),Q(0),N(2),T(0),S(4));or51: or5 port map(S(0),S(1),S(2),S(3),S(4),D(3));DFF1: DFF port map(D(3),Clk,Q(3),QN(3));and52: and5 port map(QN(3),QN(2),QN(1),Q(0),Sel11,S(5));and73: and7 port map(QN(3),QN(2),Q(1),QN(0),N(5),S50e,N(7),S(6));and74: and7 port map(QN(3),QN(2),Q(1),QN(0),N(5),N(6),S50m,S(7));and75: and7 port map(QN(3),QN(2),Q(1),Q(0),N(8),N(9),S60m,S(8));and76: and7 port map(QN(3),Q(2),QN(1),QN(0),N(11),N(12),S65m,S(9));and53: and5 port map(QN(3),Q(2),Q(1),QN(0),CA,S(10));and77: and7 port map(QN(3),Q(2),Q(1),Q(0),Sel01,N(3),N(4),S(11));or71: or7 port map(S(5),S(6),S(7),S(8),S(9),S(10),S(11),D(2));DFF2: DFF port map(D(2),Clk,Q(2),QN(2));and54: and5 port map(QN(3),QN(2),QN(1),Q(0),Sel01,S(12));and55: and5 port map(QN(3),QN(2),QN(1),Q(0),Sel10,S(13));and78: and7 port map(QN(3),QN(2),Q(1),QN(0),N(5),N(6),S50m,S(14));and79: and7 port map(QN(3),QN(2),Q(1),Q(0),N(8),N(9),S60m,S(15));xor22: xor2 port map(S65e,S65m,T(1));and64: and6 port map(QN(3),Q(2),QN(1),Q(0),N(11),T(1),S(16));and56: and5 port map(QN(3),Q(2),Q(1),QN(0),CA,S(17));and710: and7 port map(QN(3),Q(2),Q(1),Q(0),N(2),N(3),Sel11,S(18));or72: or7 port map(S(12),S(13),S(14),S(15),S(16),S(17),S(18),D(1));DFF3: DFF port map(D(1),Clk,Q(1),QN(1));and65: and6 port map(QN(3),QN(2),QN(1),QN(0),Mny,N(1),S(19));and57: and5 port map(QN(3),QN(2),QN(1),Q(0),Sel10,S(20));and711: and7 port map(QN(3),QN(2),Q(1),QN(0),N(5),S50e,N(7),S(21));and712: and7 port map(QN(3),QN(2),Q(1),Q(0),N(8),S60e,N(10),S(22));and58: and5 port map(QN(3),Q(2),Q(1),QN(0),CA,S(23));xor23: xor2 port map(Sel01,Sel10,T(2));and66: and6 port map(QN(3),Q(2),Q(1),Q(0),N(4),T(2),S(24));or61: or6 port map(S(19),S(20),S(21),S(22),S(23),S(24),D(0));DFF4: DFF port map(D(0),Clk,Q(0),QN(0));and41: and4 port map(QN(3),Q(2),QN(1),Q(0),Rpp);xor24: xor2 port map(Sel01,Sel10,T(3));xor25: xor2 port map(T(3),Sel11,T(4));and59: and5 port map(T(4),QN(3),Q(2),Q(1),Q(0),Rch);and42: and4 port map(Q(3),QN(2),QN(1),QN(0),Rac);and43: and4 port map(Q(3),QN(2),QN(1),Q(0),Rck);and44: and4 port map(Q(3),QN(2),Q(1),QN(0),Rcp);end vm_structural;

  19. Sum<50c Sum Signals Generation Block Nickel Sum=50c Dime Sum>50c Quarter Sum<60c Dollar Sum=60c Pepsi Sum>60c Cookies Sum<65c Chips Sum=65c Sum>65c FIGURE 5

  20. entity sum isport(clk,M3,M2,M1,M0,sel2,sel1,sel0:in bit; • s8,s7,s6,s5,s4,s3,s2,s1,s0:out bit);end sum;architecture sum_bhv of sum is signal sum:integer:=0; --initially sum=0 signal M:bit_vector(3 downto 0); begin M<=M3&M2&M1&M0; process(clk,M) begin if clk='1' and clk'event then • case M is when "1000" => • sum<=sum+1; when "0100" => • sum<=sum+2; when "0010" => • sum<=sum+5; when "0001" => sum<=sum+20; when others => null; • end case; end if; end process; process(clk) begin if sel2='1' then if sum<10 then s8<='1';s7<='0';s6<='0'; end if; --sum<50c if sum=10 then s7<='1';s8<='0';s6<='0'; end if; --sum=50c if sum>10 then s6<='1';s8<='0';s7<='0'; end if; --sum>50c elsif sel1='1' then if sum<12 then s5<='1';s4<='0';s3<='0'; end if; --sum<60c if sum=12 then s4<='1';s5<='0';s3<='0'; end if; --sum=60c if sum>12 then s3<='1';s4<='0';s5<='0'; end if; --sum>60c elsif sel0='1' then if sum<13 then s2<='1';s1<='0';s0<='0'; end if; --sum<65c if sum=13 then s1<='1';s2<='0';s0<='0'; end if; --sum=60c if sum>13 then s0<='1';s1<='0';s2<='0'; end if; --sum>65c end if; end process; end sum_bhv;

  21. BEHAVIOR PROGRAM FOR MAIN BLOCK • entity vm is port(Mny,Rtn,Sel01,Sel10,Sel11,S50l,S50e,S50m,S60l,S60e,S60m,S65l, • S65e,S65m,CA,Clk:in bit;Rpp,Rck,Rcp,Rac,Rch: out bit);end vm; • architecture vm_bhv of vm is signal s,ns: integer:=0; begin process(s,Mny,Rtn,Sel01,Sel10,Sel11,S50l,S50e,S50m,S60l,S60e,S60m, • S65l,S65e,S65m,CA) begin case s is when 0=> if Mny='0' and Rtn='0' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=0;end if; if Mny='1' and Rtn='0' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=1;end if; if Mny='0' and Rtn='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=8;end if; when 1=> if Sel01='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=2;end if; if Sel10='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=3;end if; if Sel11='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=4;end if; when 2=> if S50l='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=0;end if; if S50e='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=5;end if; if S50m='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=6;end if; when 3=> if S60l='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=0;end if; if S60e='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=9;end if; if S60m='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=6;end if;

  22. when 4=> • if S65l='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=0;end if; if S65e='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=10;end if; if S65m='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=6;end if; • when 5=> Rpp<='1';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=0; • when 6=> • if CA='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=7;end if; if CA='0' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=8;end if; • when 7=> • if Sel01='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='1';ns<=5;end if; if Sel10='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='1';ns<=9;end if; if Sel11='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='1';ns<=10;end if; • when 8=> Rpp<='0';Rck<='0';Rcp<='0';Rac<='1';Rch<='0';ns<=0; when 9=> Rpp<='0';Rck<='1';Rcp<='0';Rac<='0';Rch<='0';ns<=0; when 10=> Rpp<='0';Rck<='0';Rcp<='1';Rac<='0';Rch<='0';ns<=0; when others=> null; end case; end process; process(Clk) begin if Clk='1' then s<=ns; end if; end process; end vm_bhv;

  23. STRUCTURAL PROGRAM FOR VENDING MACHINE CONTROLLER entity newvm is port(Mny,Rtn,Sel01,Sel10,Sel11,nickel,dime,quarter,dollar,CA,Clk:in bit; Rpp,Rck,Rcp,Rac,Rch: out bit); end newvm; architecture newvm_structural of newvm is signal sm:bit_vector(8 downto 0); component sumport(clk,M3,M2,M1,M0,sel2,sel1,sel0:in bit; s8,s7,s6,s5,s4,s3,s2,s1,s0:out bit) end component; component vmport(Mny,Rtn,Sel01,Sel10,Sel11,S50l,S50e,S50m,S60l,S60e,S60m,S65l,S65e,S65m, CA,Clk:in bit; Rpp,Rck,Rcp,Rac,Rch: out bit); end component; beginsum1:sum portmap (Clk,nickel,dime,quarter,dollar,Sel01,Sel10,Sel11, sm(8),sm(7), sm(6),sm(5),sm(4),sm(3),sm(2),sm(1),sm(0));vm1: vm port map (Mny,Rtn,Sel01,Sel10,Sel11,sm(8),sm(7),sm(6), sm(5),sm(4), sm(3), sm(2),sm(1), sm(0),CA,Clk,Rpp,Rck,Rcp,Rac,Rch); end newvm_structural;

  24. PLOT 3 STRUCTURAL ARCHITECTURE WAVEFORM FOR RELEASE OF PEPSI

  25. PLOT 4 STRUCTURAL ARCHITECTURE WAVEFORMS FOR RETURNING ALL MONEY

  26. QUESTIONS ????

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