Ee435 final project 9 bit sar adc
Sponsored Links
This presentation is the property of its rightful owner.
1 / 35

EE435 Final Project: 9-Bit SAR ADC PowerPoint PPT Presentation


  • 61 Views
  • Uploaded on
  • Presentation posted in: General

EE435 Final Project: 9-Bit SAR ADC. Curtis Mayberry, Kyle Slinger, Yuan Ji( 计元 ). 9-Bit SAR ADC. Requirements 9 bits of resolution INL ± 1 LSB DNL ± 1 LSB Speed > 0.2 MSPS Power < 20 mW Area < 1 mm^2. System Design. SAR ADC system level design. System Level Design.

Download Presentation

EE435 Final Project: 9-Bit SAR ADC

An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -

Presentation Transcript


EE435 Final Project: 9-Bit SAR ADC

Curtis Mayberry, Kyle Slinger, Yuan Ji(计元)


9-Bit SAR ADC

Requirements

  • 9 bits of resolution

  • INL ± 1 LSB

  • DNL ± 1 LSB

  • Speed > 0.2 MSPS

  • Power < 20 mW

  • Area < 1 mm^2


System Design

SAR ADC system level design


System Level Design


Charge Redistribution DAC Design

  • Charge Redistribution (Q=CV and Q is conserved)

  • 2 cycles sampling

  • Estimate bit by bit


9-bit SAR ADC

Final Schematic


9-bit SAR ADC

Switch Device Sizing

Transmission Gate Style Switch Used for Vin Tracking

Single Transistor Switches Used for Vdd and Vss

Smallest switch nmos=1.5um wide by 600nm long

Smallest switch pmos=4.5um wide by 600nm long

Sizes increase proportionally to capacitor sizes

4 sizes used. Largest can drive largest capacitor full range in 50ns.


9-bit SAR ADC

Switches


9-bit SAR ADC

Switch Testing

Switching with the largest switch and largest load capacitor

Approximately 50 ns required for maximum rise and fall time.

This corresponds to 20 MSPS


9-bit SAR ADC

Switch Testing


9-bit SAR ADC

Switch Testing


9-bit SAR ADC

Capacitor Array


9-bit SAR ADC

Comparator


9-bit SAR ADC

Comparator Performance

  • DC Gain: 79.91 dB

  • Resolution: 0.5 mV

  • 3 dB Bandwidth: 26.87 MHz

  • Propagation Delay(1 LSB step): 6.5 ns

  • Hysteresis Voltage: +- 1.815 mV

  • Power Consumption: 2 mW


9-bit SAR ADC

Comparator Design Strategy


9-bit SAR ADC

Comparator 1st Stage


9-bit SAR ADC

Comparator 2nd Stage


9-bit SAR ADC

Comparator Hysteresis


9-bit SAR ADC

Comparator 3rd Stage


9-bit SAR ADC

Propagation Delay(1 LSB step)


9-bit SAR ADC

Propagation Delay vs. Overdrive Amplitude


Digital SAR Logic

HDL design

HDL simulation in Modelsim

Elaboration Results

Synthesis Results

Initial Verification Test Bench

Final Implementation


FSM Diagram


HDL simulation Testbench Scenario 1


HDL simulation Testbench Scenario 2


HDL simulation Results


Elaboration


Synthesized Digital Control


Final Digital Schematic


Spectral and Static Performance

Spectral analysis, INL, and DNL


INL, DNL, and Spectral Testing Test Bench


Spectrum Analysis of the ADC

  • Signal Frequency : 312.5 KHz

  • Sampling Frequency: 946.745 Khz

  • M=512

  • K=169


DNL: First fifth of code

  • Ran for 100us of a 543us ramp

  • Decreased run time

  • 0.99 DNL over this range


INL over 100us from 0 to FS code

  • 6.4 LSB INL

  • 11 LSB offset


INL and DNL over 543us, covering FS

INL = 15.3 LSB INL index: 4.692 *10^-4

DNL = 1.99 LSB DNL time: 1.122 *10^-4


  • Login