EE435 Final Project: 9-Bit SAR ADC. Curtis Mayberry, Kyle Slinger, Yuan Ji( 计元 ). 9-Bit SAR ADC. Requirements 9 bits of resolution INL ± 1 LSB DNL ± 1 LSB Speed > 0.2 MSPS Power < 20 mW Area < 1 mm^2. System Design. SAR ADC system level design. System Level Design.
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Curtis Mayberry, Kyle Slinger, Yuan Ji(计元)
SAR ADC system level design
Switch Device Sizing
Transmission Gate Style Switch Used for Vin Tracking
Single Transistor Switches Used for Vdd and Vss
Smallest switch nmos=1.5um wide by 600nm long
Smallest switch pmos=4.5um wide by 600nm long
Sizes increase proportionally to capacitor sizes
4 sizes used. Largest can drive largest capacitor full range in 50ns.
Switching with the largest switch and largest load capacitor
Approximately 50 ns required for maximum rise and fall time.
This corresponds to 20 MSPS
Comparator Design Strategy
Comparator 1st Stage
Comparator 2nd Stage
Comparator 3rd Stage
Propagation Delay(1 LSB step)
Propagation Delay vs. Overdrive Amplitude
Digital SAR Logic
HDL simulation in Modelsim
Initial Verification Test Bench
Spectral and Static Performance
Spectral analysis, INL, and DNL
INL = 15.3 LSB INL index: 4.692 *10^-4
DNL = 1.99 LSB DNL time: 1.122 *10^-4