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2-PAD Digital Beamformer Chris Shenton 11 th October 2007

2-PAD Digital Beamformer Chris Shenton 11 th October 2007. Objectives. Implement an example of a fully digital beamforming system. Initially a 4x4 receiving element array, scalable up to 8x8 elements. Can go much bigger with more hardware. Set modest initial performance targets.

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2-PAD Digital Beamformer Chris Shenton 11 th October 2007

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  1. 2-PAD Digital BeamformerChris Shenton11th October 2007

  2. Objectives Implement an example of a fully digital beamforming system. Initially a 4x4 receiving element array, scalable up to 8x8 elements. Can go much bigger with more hardware. Set modest initial performance targets. With expectations to do A LOT better as we explore optimisation options. Fully scalable architecture with a high degree of platform independence. Use it to develop software methodology.

  3. 2-PAD Beamformer Processing Architecture Large number of simple high performance processing elements; Connected together via very high bandwidth links. Processing element means; on-chip – thread unit or similar operational unit off-chip – multiple devices Concept is valid for both intra-chip and inter-chip communications Key Point: The problem is data movement NOT MFLOPS.

  4. Continued... • Software development methodologies for multi-processor systems are not yet defined but are happening (e.g PS3 Cell Processor). • Difficult problem will have to be solved by the major silicon vendors, we will see the benefit of this effort by intercepting these new methods. • This is the future of computing for both scientific and mass market computing.

  5. Continued... We need to obtain very high density processing to meet power and cost objectives. Possible implementation options include; ASIC – Very high density, lowest power, lowest cost FPGA – Flexibilty, medium density, high power, high cost. MPU/GPU – Flexibility, medium density, medium power, medium cost Start simple with simple Units of Design deployed sparsely on commercially available processor technology.

  6. Increasing The Processing Capacity of 2-PAD. • Scalable Architecture in 3 dimensions • 2-PAD Initial implementation has low processing density vs hardware resource. • Blue area represents initial 4x4 element design • Yellow area represents scale up to 8x8 elements.

  7. So What Are We Building Then?

  8. Data Acquisition Card

  9. Processor Interface Card.

  10. Summary • Digital Beamforming is as much an issue of inter-processor bandwidth than raw FLOPs. • Cost of Multi-core Processors will fall in the medium term. • Improvements in software development methodologies will have to happen. • 2-PAD Will demonstrate fundamental architectural concepts with options for future cost & power reduction.

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