Virtual memory
This presentation is the property of its rightful owner.
Sponsored Links
1 / 17

Virtual Memory PowerPoint PPT Presentation


  • 57 Views
  • Uploaded on
  • Presentation posted in: General

Virtual Memory. Virtual Memory: Topics. Why virtual memory? Virtual to physical address translation Page Table Translation Lookaside Buffer (TLB). Another View of Memory Hierarchy. Upper Level. Regs. Faster. Instructions, Operands. Cache. {. Blocks. Thus far. L2 Cache. Blocks.

Download Presentation

Virtual Memory

An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -

Presentation Transcript


Virtual memory

Virtual Memory


Virtual memory topics

Virtual Memory: Topics

  • Why virtual memory?

  • Virtual to physical address translation

  • Page Table

  • Translation Lookaside Buffer (TLB)


Another view of memory hierarchy

Another View of Memory Hierarchy

Upper Level

Regs

Faster

Instructions, Operands

Cache

{

Blocks

Thus far

L2 Cache

Blocks

Memory

{

Next:

Virtual

Memory

Pages

Disk

Larger

Files

Lower Level

Tape


Why virtual memory

Why Virtual Memory?

  • Today computers run multiple processes, each with its own address space

  • Too expensive to dedicate a full-address-space worth of memory for each process

  • Principle of Locality

    • allows caches to offer speed of cache memory with size of DRAM memory

    • DRAM can act as a “cache” for secondary storage (disk)  Virtual Memory

  • Virtual memory – divides physical memory into blocks and allocate them to different processes


Mapping virtual to physical memory

Virtual Memory

Physical Memory

0

A

0

4 KB

B

B

4 KB

8 KB

C

8 KB

A

12 KB

D

12 KB

16 KB

C

20 KB

Disk

D

24 KB

28 KB

Mapping Virtual to Physical Memory

  • Program with 4 pages (A, B, C, D)

  • Any chunk of Virtual Memory assigned to any chuck of Physical Memory (“page”)


Virtual memory terminology

Virtual Memory Terminology

  • Virtual Address

    • address used by the programmer; CPU produces virtual addresses

  • Virtual Address Space

    • collection of such addresses

  • Memory (Physical or Real) Address

    • address of word in physical memory

  • Memory mapping or address translation

    • process of virtual to physical address translation

  • More on terminology

    • Page or Segment Block

    • Page Fault or Address Fault  Miss


Virtual to physical addr translation

Virtual to Physical Addr. Translation

  • Each program operates in its own virtual address space

  • Each is protected from the other

  • OS can decide where each goes in memory

  • Combination of HW + SW provides virtual  physical mapping

Program

operates in

its virtual

address

space

Physical

memory

(incl. caches)

physical

address

(inst. fetch

load, store)

virtual

address

(inst. fetch

load, store)

HW

mapping


Virtual memory mapping function

...

31

10

9

0

...

Virtual Page No. Offset

Phys. Page No. Offset

Virtual Memory Mapping Function

  • Use table lookup (“Page Table”) for mappings: Virtual Page number is index

  • Virtual Memory Mapping Function

    • Physical Offset = Virtual Offset

    • Physical Page Number (P.P.N. or “Page frame”)= PageTable[Virtual Page Number]

Virtual Address

translation

29

0

10

9

...

...

Physical Address


Address mapping page table

Page Table

Base Reg

Address Mapping: Page Table

Virtual Address:

virtual page no.

offset

Page Table

Access

Rights

Physical Page

Number

Valid

index

into

Page

Table

...

offset

physical page no.

Physical Address


Page table entry pte format

Page Table Entry (PTE) Format

  • Valid bit indicates if page is in memory

    • OS maps to disk if Not Valid (V = 0)

  • Contains mappings for every possible virtual page

  • If valid, also check if have permission to use page: Access Rights (A.R.) may be Read Only, Read/Write, Executable

Page Table

P.T.E.


Typical tlb format

Typical TLB Format

  • Tag: Portion of virtual address

  • Data: Physical Page number

  • Dirty: since use write back, need to know whether or not to write page to disk when replaced

  • Ref: Used to help calculate LRU on replacement

  • Valid: Entry is valid

  • Access rights: R (read permission), W (write perm.)


Translation look aside buffers

Translation Look-Aside Buffers

  • TLBs usually small, typically 128 - 256 entries

  • Like any other cache, the TLB can be fully associative, set associative, or direct mapped

hit

PA

VA

miss

TLBLookup

Main Memory

Processor

Cache

hit

miss

Data

Translation


The big picture

The Big Picture

Virtual address

TLB access

No

Yes

TLB hit?

Yes

No

try to read from PT

Write?

try to read from cache

Yes

Set in TLB

No

page fault?

No

cache/buffer mem. write

Yes

Cache hit?

replace page from disk

TLB miss stall

Deliver data to CPU

cache missstall


Virtual memory

Translation Look-Aside Buffers

  • TLB is usually small, typically 32-4,096 entries

  • Like any other cache, the TLB can be fully associative, set associative, or direct mapped

data

data

virtualaddr.

physicaladdr.

TLB

Cache

miss

Main

Memory

hit

hit

Processor

miss

PageTable

Disk

Memory

OS FaultHandler

page fault/protection violation


Virtual memory

DECStation 3100/MIPS R2000

3

1

3

0

2

9

1

5

1

4

1

3

1

2

1

1

1

0

9

8

3

2

1

0

Virtual Address

V

i

r

t

u

a

l

p

a

g

e

n

u

m

b

e

r

P

a

g

e

o

f

f

s

e

t

2

0

1

2

V

a

l

i

d

D

i

r

t

y

P

h

y

s

i

c

a

l

p

a

g

e

n

u

m

b

e

r

T

a

g

TLB

T

L

B

h

i

t

64 entries, fully associative

2

0

P

h

y

s

i

c

a

l

p

a

g

e

n

u

m

b

e

r

P

a

g

e

o

f

f

s

e

t

Physical Address

P

h

y

s

i

c

a

l

a

d

d

r

e

s

s

t

a

g

C

a

c

h

e

i

n

d

e

x

B

y

t

e

1

4

2

1

6

o

f

f

s

e

t

T

a

g

D

a

t

a

V

a

l

i

d

Cache

16K entries, direct mapped

3

2

D

a

t

a

C

a

c

h

e

h

i

t


Parallel address translation tlb and cache access

Parallel Address translation (TLB and Cache access)

Example:

L1-8K, L2-4M, Page-8K, cl-64B, VA-64b, PA-41b


Things to remember

Things to Remember

  • Apply Principle of Locality Recursively

  • Manage memory to disk? Treat as cache

    • Included protection as bonus, now critical

    • Use Page Table of mappings vs. tag/data in cache

  • Spatial locality means Working Set of pages is all that must be in memory for process to run

  • Virtual memory to Physical Memory Translation too slow?

    • Add a cache of Virtual to Physical Address Translations, called a TLB

  • Need more compact representation to reduce memory size cost of simple 1-level page table (especially 32  64-bit address)


  • Login