Vip1 a 3d integrated circuit for pixel applications in high energy physics
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VIP1: a 3D Integrated Circuit for Pixel Applications in High Energy Physics. Jim Hoff*, Grzegorz Deptuch, Tom Zimmerman, Ray Yarema - Fermilab * [email protected] Vertical Integration (a.k.a. 3D Integration)– What is it?. Several active semiconductor layers “independently” designed

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VIP1: a 3D Integrated Circuit for Pixel Applications in High Energy Physics

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VIP1: a 3D Integrated Circuit for Pixel Applications in High Energy Physics

Jim Hoff*, Grzegorz Deptuch, Tom Zimmerman, Ray Yarema - Fermilab

* [email protected]


Vertical Integration (a.k.a. 3D Integration)– What is it?

  • Several active semiconductor layers “independently” designed

    • Not necessarily the same function

    • Not necessarily the same technology

  • Thinned

  • Bonded together

  • Interconnected to one another with deep vias


3D vias

8.2 µm

7.8 µm

6.0 µm

Vertical Integration (a.k.a. 3D Integration)– What is it?


Vertical Integration (a.k.a. 3D Integration)– What is it?

J. Joly, LETI

  • Industry’s Interest in Vertical Integration

  • Moore’s Law

  • Reduce R, L, C for higher speed

  • Reduce chip I/O pads

  • Provide increased functionality

  • Reduce interconnect power and crosstalk

  • HEP’s Interest in Vertical Integration

  • Reduced Mass in the Beamline

  • Selectable detector and readout technologies

  • Increased functionality per unit area at a given feature size


VIP1: What is it?

The VIP1 is a 64x64 demonstrator version of a 1k x 1k readout chip for ILC pixel vertex applications. It is designed to conform to ILC standards as they are understood today.

Features

  • 20 mm x 20 mm pixel size

  • Binary (hit/no hit) information with analog hit information to improve resolution

  • Double Correlated Sampling

  • Both analog and digital time stamping, each individually capable of resolving 32 time steps per bunch train.

  • Readout between bunch trains

  • Data sparsification with pipelined token passing

  • A single point-to-point serial output line

  • Design for megapixel array, but layout a 64x64 array

  • Low power (assuming power pulsing is used)

  • A Test input per pixel


VIP1: Overall System Architecture


VIP1: Pixel Cell Block Diagram


Inter-tier vias are substantial

Logical versus physical division of function

Layout on one tier impacts layout on other tiers.

Conversion to a 3D architecture


X, Y line

control

OR, SR FF

Tier 3

analog

Token

passing logic

3D

vias

D FF

Tier 2

Time

Stamp

Test input

circuit

Tier 1

Data

sparsification

The Pixel Cell on Tier 1

  • SR-ff for hit storage for the duration of the pulse train.

  • OR to allow universal read

  • Conservative, static, edge-triggered DFF in data sparsification.

  • Dynamic edge-triggered DFF for test input pulses

  • 65 transistors


b3

Analog

T. S.

Tier 3

analog

3D

vias

b2

Tier 2

Time

Stamp

b1

b4

b0

Tier 1

Data

sparsification

The Pixel Cell on Tier 2

  • 5 bit digital timestamp latched in the pixel from a Gray Code counter on the periphery of Tier 2

  • Analog time stamp resolution to be determined, but expecting 5 bits

  • Time stamps can be used in alone or in series to create a 10 bit time stamp.

  • 72 transistors


Schmitt

Trigger+NOR

Integrator

Discriminator

Tier 3

analog

3D

vias

Tier 2

Time

Stamp

CTI

DCS + Readout

Tier 1

Data

sparsification

The Pixel Cell on Tier 3

  • Integrator

  • Double correlated sample plus readout

  • Discriminator

  • Chip scale programmable threshold input

  • Capacitive test input (CTI)

  • 38 transistors

  • 2 vias


3D Stacking (of a single pixel) with Vias (step 1)

Tier 1 pixel circuit

Buried oxide (BOX), 400 nm thick

2000 ohm-cm p-type substrate


3D Stacking (of a single pixel) with Vias (step 2)

Bond tier 2 to tier 1

Tier 2

Tier 1


3D Stacking (of a single pixel) with Vias (step 3)

Form 3 vias, 1.5 x 7.3 µm,

through Tier 2 to Tier 1


3D Stacking (of a single pixel) with Vias (step 4)

Bond tier 3 to tier 2

Tier 3

Tier 2


3D Stacking (of a single pixel) with Vias (step 5)

Form 2 vias, 1.5 x 7.3 µm,

through tier 3 to tier 2


A 64x64 Array with Perimeter Logic

  • Perimeter circuitry for the ILC Demonstrator chip occupies a small amount of space.

  • Area for the perimeter logic could be reduced in future designs.

Blow up of

corner of

array

64 x 64 array with perimeter logic


Status

  • The design was submitted in October of last year. It was due in August of this year.

  • We expect delivery any day and hope to present experimental results in the conference record or in a TNS paper.

  • This design was fabricated as part of a multi-project wafer run supported as a DARPA R&D effort. This was the second such run.

  • A third MPW run is planned for next year.


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