VIP1: a 3D Integrated Circuit for Pixel Applications in High Energy Physics. Jim Hoff*, Grzegorz Deptuch, Tom Zimmerman, Ray Yarema - Fermilab * [email protected] Vertical Integration (a.k.a. 3D Integration)– What is it?. Several active semiconductor layers “independently” designed
Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.
VIP1: a 3D Integrated Circuit for Pixel Applications in High Energy Physics
Jim Hoff*, Grzegorz Deptuch, Tom Zimmerman, Ray Yarema - Fermilab
J. Joly, LETI
The VIP1 is a 64x64 demonstrator version of a 1k x 1k readout chip for ILC pixel vertex applications. It is designed to conform to ILC standards as they are understood today.
Inter-tier vias are substantial
Logical versus physical division of function
Layout on one tier impacts layout on other tiers.
X, Y line
OR, SR FF
DCS + Readout
Tier 1 pixel circuit
Buried oxide (BOX), 400 nm thick
2000 ohm-cm p-type substrate
Bond tier 2 to tier 1
Form 3 vias, 1.5 x 7.3 µm,
through Tier 2 to Tier 1
Bond tier 3 to tier 2
Form 2 vias, 1.5 x 7.3 µm,
through tier 3 to tier 2
Blow up of
64 x 64 array with perimeter logic