Threats and challenges in fpga security
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Threats and Challenges in FPGA Security. Ted Huffmire Naval Postgraduate School December 10, 2008. Overview. Problem Areas. Foundry Trust. Physical Attacks. Design Tools. Design Theft. System Assurance. Attacks. Trojan horse Backdoor Kill switch. Probing Sand and Scan

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Threats and challenges in fpga security

Threats and Challenges in FPGA Security

Ted Huffmire

Naval Postgraduate School

December 10, 2008


Overview

Overview

Problem Areas

Foundry

Trust

Physical

Attacks

Design

Tools

Design

Theft

System

Assurance

Attacks

Trojan horse

Backdoor

Kill switch

Probing

Sand and Scan

Side Channels

Data Remanence

Covert channels

Side channels

Bypass

Cloning

Reverse engineer

Readback attack

DoS

Authentication

Complex designs

Solutions

Trusted foundries

FPGAs

X-Ray Inspection

Sand and Scan

Tamper sensing

Adding noise

Degaussing

Logical isolation

Tracing wires

Sanitization

Continuous power

Encrypt bitstream

Watermarking

Authentication

Reference monitor

Defense in depth

User training

Security usability

Future Research

All of supply chain

Lessons from S/W

Red teams

Side channels

Trusted tools

Verification

Languages

CM

High-assurance

Partial reconfig

PUFs

High-assurance

CMPs

Tagging

Dynamic security


Reconfigurable hardware

DRAM

DRAM

Reference

Monitor

DRAM

DRAM

DRAM

DRAM

CPU Core

DRAM

DRAM

μP

DRAM

DRAM

DRAM

DRAM

AES

Crypto Core

CPU Core

SDRAM (off-chip)

μP

FPGA Chip

Reconfigurable Hardware


Protection alternatives

Reconfigurable Protection

Separation Kernels

Separate Processors

app1

app2

app3

ReferenceMonitor

app1

DRAM

gate

keeper

gate

keeper

gate

keeper

kernel

DRAM

app2

DRAM

app2

app1

app3

DRAM

DRAM

app3

DRAM

DRAM

DRAM

DRAM

DRAM

DRAM

DRAM

DRAM

DRAM

DRAM

DRAM

DRAM

DRAM

DRAM

DRAM

DRAM

DRAM

DRAM

DRAM

DRAM

DRAM

DRAM

DRAM

DRAM

DRAM

Physical

Software

Spatial

Temporal

Protection Alternatives


Design flows

Design Flows


Intertwined cores

Intertwined Cores


Moats

DRAM

DRAM

Reference

Monitor

DRAM

DRAM

DRAM

DRAM

CPU Core

DRAM

DRAM

DRAM

DRAM

DRAM

DRAM

AES

AES

Crypto Core

CPU Core

SDRAM (off-chip)

FPGA Chip

Moats


Moats 1 0

Moats 1.0


Moats 2 0

Moats 2.0


Moats and drawbridges

Moats and Drawbridges


Interconnect tracing

DRAM

DRAM

Reference

Monitor

DRAM

DRAM

DRAM

DRAM

CPU Core

DRAM

DRAM

μP

DRAM

DRAM

DRAM

DRAM

AES

Crypto Core

X

X

CPU Core

SDRAM (off-chip)

μP

FPGA Chip

Interconnect Tracing


Communication architecture

DRAM

DRAM

Arbiter/Reference Monitor

DRAM

DRAM

DRAM

DRAM

CPU Core

DRAM

DRAM

μP

DRAM

DRAM

DRAM

DRAM

AES

Crypto Core

CPU Core

SDRAM (off-chip)

μP

FPGA Chip

Communication Architecture


Memory protection

DRAM

DRAM

Reference Monitor

DRAM

DRAM

DRAM

DRAM

Reference Monitor

CPU Core

DRAM

DRAM

DRAM

DRAM

DRAM

DRAM

AES

AES

Crypto Core

X

CPU Core

X

SDRAM (off-chip)

FPGA Chip

Memory Protection


Policy compiler

Policy Compiler


Soc application

SoC Application


Questions

Questions?

  • http://faculty.nps.edu/tdhuffmi


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