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My First Nios II for Altera DE2-115 Board

My First Nios II for Altera DE2-115 Board. 數位電路實驗 TA : 吳柏辰. Author: Trumen. Outline. Hardware Design NIOS II IDE Build Flow Programming the CFI Flash. Hardware Design. Introduction.

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My First Nios II for Altera DE2-115 Board

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  1. My First Nios II for Altera DE2-115 Board 數位電路實驗 TA: 吳柏辰 Author: Trumen

  2. Outline • Hardware Design • NIOS II IDE Build Flow • Programming the CFI Flash

  3. Hardware Design

  4. Introduction • This slides provides comprehensive information that will help you understand how to create a FPGA based SOPC system implementing on your FPGA development board and run software upon it.

  5. Required Features (1/2) • The Nios II processor core is a soft-core central processing unit (CPU) that you could program onto an Altera field programmable gate array (FPGA). • This chapter illustrates you to the basic flow covering hardware creation and software building.

  6. Required Features (2/2) • The example NIOS II standard hardware system provides the following necessary components: • Nios II processor core, that’s where the software will be executed. • On-chip memory to store and run the software. • JTAG link for communication between the host computer and target. • Hardware (typically using a USB-Blaster cable). • LED peripheral I/O (PIO), be used as indicators.

  7. Creation of Hardware Design 1 2 3

  8. 1 2 same as (top-level) file name 3

  9. 1

  10. 1 2 for DE2-115 3

  11. 1 2

  12. 1 2 3 4

  13. 1 2

  14. 1(double-click) 2

  15. 1 2

  16. 1 2(double-click) 3

  17. 1 2

  18. 3 4 1 2(double-click)

  19. 1 2

  20. 3 4 2(double-click) 5 1

  21. 1(double-click) 2

  22. 1 2

  23. 3 2(double-click) 1

  24. 1 2

  25. 1

  26. 1

  27. 1 2

  28. 1

  29. 5 1 3 4 2

  30. 1 2 3 4

  31. 1

  32. moduleNiosII( clk, rst_n, led, ); inputclk, rst_n; output[7:0] led; DE2_115_QSYS DE2_115_QSYS_inst ( .clk_clk(clk), .reset_reset_n(rst_n), .led_export(led), ); endmodule

  33. 2 3 1

  34. 1 2 3

  35. 2 1 3 4

  36. 1 2

  37. 2 1 4 3

  38. 1 2 3

  39. 1 2

  40. 2 1

  41. 1 2

  42. 1 2

  43. create_clock-period20[get_portsclk] derive_clock_uncertainty set_input_delay0-clockclk[all_inputs] set_output_delay0-clock clk[all_outputs]

  44. 5 1 2 4 3 46

  45. 1

  46. 1

  47. 1

  48. When configuration is complete, the FPGA is configured with the Nios II system, but it does not yet have a C program in memory to execute.

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