Bruce Mayer, PE Registered Electrical & Mechanical Engineer BMayer@ChabotCollege.edu

1. Engineering 43 FETs-3(Field Effect Transistors) Bruce Mayer, PE Registered Electrical & Mechanical EngineerBMayer@ChabotCollege.edu

2. Learning Goals • Understand the Basic Physics of MOSFET Operation • Describe the Regions of Operation of a MOSFET • Use the Graphical LOAD-LINE method to analyze the operation of basic MOSFET Amplifiers • Determine the Bias-Point (Q-Point) for MOSFET circuits

3. Learning Goals • Analyze the I/O relationship for small-signal Amplifiers • Determine the OutPut for Various CMOS Logic Gates

4. “Common” – What does it mean? • “Common” is an electronics term that usually means a digital-GROUND of Some Sort. • Recall that in the small Signal Case that VDC Sources are effectively SHORTS to the Small-Signal “Common”, or GND Connection • Example: A “common-source” MOSFET amp has the source connected to small-signal GND somehow

5. Refined Small Signal Model • The KCL Equation for the model that accounts for the upward iD Slope in SAT • The Graphical Representation

6. Common Source Amplifier • A typical “CS” Amp Circuit

7. Common Source Amplifier • Analyze, Qualitatively the CS Amp Circuit • Recall for Caps • SHORTS to fast AC • OPENS to DC • C1 and C2 are “Coupling” capacitors • C1 couples the input to the MOSFET gate • C2 couple the Output to the Load, RL • CS connects the FET Source-Connection to GND (or Common)

8. Common Source Amplifier • Analyze, Qualitatively the CS Amp Circuit • Resistors R1, R2, RD, and RS form the Bias Network • The Bias Network is designed to set the Q-Point to allow a large swing in the output signal, vo, as a result of large input Voltage (vin = vgs) Changes. • The FET MUST Remain in SATURATION during the entire Swing

9. CS-Amp Small Signal Model • Recall the Small Signal FET Model from Last time • Note that Caps & DC-Srcs are Shorts • Yields the small signal Model

10. LargeSmallSignal Model → ShortTo ACSignals

11. CS-Amp Voltage Gain • By Parallel Resistors • Use these equivalent Resistances to simplify the small signal Ckt • Also define vin and vo for the equivalent circuit

12. CS-Amp Voltage Gain • By V-Divider on Left Loop • On Right (OutPut) Loop • Thus by Ohm • Also • Thus Av:

13. CS-Amp input Resistance • Recall R = ∆V/∆I • For the Common Source Amp • From Before • Thus Rin

14. CS Amp OutPut Resistance • To find the OUTput Resistance • Set v(t) = 0 • i.e.; it becomes a SHORT • Disconnect Load RL • Find R Looking into the RL terminals • This Produces the Ro circuit • Since vgs = 0 V, then gmvgs = 0 amps • i.e.; the dependent current source is OPEN • Thus can Find Ro by Parallel combination

15. Check by Thévenin:

16. Check by Thévenin:

17. Source Follower Circuit

18. Source Follower Circuit • Notes on SF Ckt • R is the internal (Thévenin)resistance of the input source • C1 and C2 are Coupling Capacitors • They are SHORTS to the Small Signal • R1, R2, and RS form the Bias (Q-Pt) Network • In Small-Signal vd connected to GND

19. SF Large Signal Model

20. SF Large Signal Model

21. Source Follower Circuit • Note that in this case the DRAIN is connected to DC-Source VDD; a SHORT to the Small Signal. • Then the Small Signal Model

22. SF Small Signal Model

23. Source Follower Circuit • Again, Equivalent Resistances • Note that in this Circuit the Drain is at the Bottom (GND’d), and Source is at the Top • Then the Equivalent Model • By Ohm on the Rt

24. Source Follower Circuit • Note that the • Source is at the vo Voltage • Gate is at the vin Voltage as iin =0 • Then by KVL on a clever Loop

25. Source Follower Circuit • But recall • Substitute out vo in the previous Eqn • Then the Voltage Gain (amplification) • Factor out vgs • Cancelling vgs Find in the Small Signal Case:

26. Source Follower Circuit • The Input Resistance • For Ro • Set v(t) = 0 • i.e.; Short it • Remove RL • Apply a Voltage PROBE to SD Connections • The probed Circuit • Then Ro =vx/ix • Note that vin = 0 (no PwrSrc) → G-terminal is at GND

27. Source Follower Circuit • And vs fixed at vxso • Now KCL at Top-Right node (in = out) • Subbing out vgs • Collecting Terms • Then Ro =vx/ix

28. Recall from Chp7 Logic Gates • Truth Tables Describe the I/O behavior of Logic Gates, but NOT how they are constructed • Most Modern Logic gates are built from collections of MOSFETS

29. Alternative Symbols for MOSFETs • nMOSFETs • “ON”: when VGSPOSITIVE • pMOSFETs • “ON”: when VGSNEGATIVE

30. Alternative Symbol Meaning • The Arrow shows the direction of Current flow in SOURCE Connection • In an nFET current flows: Drain→Source • Current flows OUT of the source when FET On • In a pFET current flows: Source→Drain • Current flows Into the Source when FET On nFET pFET

31. CMOS  What is it? • “CMOS” it the technology used in Digital Integrated Circuits such as MicroProcessors. The Meaning • C ≡ Complementary ← The key • M ≡ Metal • O ≡ Oxide • S ≡ Silicon

32. Complementary Logic • In Perfect Complementary Logic circuits every nFET (or pFET) has it’s opposite, or complementary pFET (or nFET) • Example: CMOS Inverter

33. Switch Model for CMOS Logic Ckts • The INPUT to CMOS Logic Circuits is assumed to be DIGITAL; that is the Input is one of • Hi (usually VDD) ORLo (usually GND) • Example: CMOS Inverter (a) Input isLo;Output is Hi (a) Input isHi:Output is Lo

34. CMOS Inverter Summarized • Note that SOURCE and BODY are “tied Together” • This is very typical for Enhancement Mode MOSFETS • A third Alternative seen in Logic Ckt Analysis is the “Invert BUBBLE” on the pFET nFET pFET

35. Invert-Bubble Inverter Circuit • Using the Inversion-Bubble facilitates drawing and analysis of CMOS Logic Circuits. • The “Bubble” Version of the Inverter ckt

36. CMOS Voltage Levels for 1 & 0 • As discussed previously a “digital” 1 or 0 is represented by a RANGE (analog) of Voltage Levels. For typical CMOS

37. CMOS NAND Gate • NAND: All Hi → Lo, else Hi     Basic Circuit A-Hi & B-LoVout Connected to VDD BOTH A & B HiVout Connected to GND

38. CMOS NAND “Switch” Analysis • Drawing the FETs as switches can Speed and/or Clarify the output analysis    

39. CMOS NAND “Bubble” Analysis

40. CMOS NOR Gate • NOR: Any Hi → Lo, else Hi     Basic Circuit A-Hi & B-LoVout Connected to GND BOTH A & B LoVout Connected to VDD

41. CMOS NOR Switch Analysis • NOR: Any Hi → Lo, else Hi

42. WhiteBoard Work • Determine the TRUTH Table for the CMOS Logic Gate Below

43. All Done for Today TypicalCMOS gateI/O Curve • CMOS Inverter

44. Engineering 43 AppendixOther CMOS Gates Bruce Mayer, PE Registered Electrical & Mechanical EngineerBMayer@ChabotCollege.edu

46. DC Srcs SHORTS in Small-Signal • In the small-signal equivalent circuit DC voltage-sources are represented by SHORT CIRUITS; since their voltage is CONSTANT, the exhibit ZERO INCREMENTAL, or SIGNAL, voltage • Alternative Statement: Since a DC Voltage source has an ac component of current, but NO ac VOLTAGE, the DC Voltage Source is equivalent to a SHORT circuit for ac signals

47. Ways to Make 1’s & 0’s

48. 3-Input NAND Ref: 2010-005. Wakerly - Chapter_03 - logic gates_VERYGood.pptx

49. CMOS Buffer (Unity Gain) • Inverters in SERIES

50. AND Gate