Enabling high precision high performance dsp variable precision dsp architecture
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Enabling High-Precision, High-Performance DSP Variable-Precision DSP Architecture. 2010 Technology Roadshow. Agenda. DSP system design trend Altera DSP architecture (28 nm) Summary. Key DSP Design Trend. 9-Bit Precision. Floating-point Precision. TeraFLOPs. 100 GMACs. Video

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Enabling High-Precision, High-Performance DSP Variable-Precision DSP Architecture

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Enabling high precision high performance dsp variable precision dsp architecture

Enabling High-Precision, High-Performance DSPVariable-Precision DSP Architecture

2010 Technology Roadshow


Agenda

Agenda

  • DSP system design trend

  • Altera DSP architecture (28 nm)

  • Summary


Key dsp design trend

Key DSP Design Trend

9-Bit Precision

Floating-point Precision

TeraFLOPs

100 GMACs

Video

Surveillance

Broadcast

Systems

Wireless

Basestations

Medical

Imaging

Military

Radar

High-Performance

Computing

Applications Moving to Variable and Higher Precisions


High precision dsp applications

High-precision DSP Applications

High-performance Computing

Military

High-precision multiply

accumulate

High-precision FIR filters

High-precision FFTs

Floating-point FFTs

Floating-point matrix

operations

Medical

Wireless

Test and Measurement


Industry s first variable precision dsp block

Industry’s First Variable-precision DSP Block

Set the Precision Dial to Match Your Application


Dsp builder advanced blockset

DSP Builder Advanced Blockset

HDL Automatically Optimized for System Clock Frequency and Latency


Dsp builder advanced blockset advantage building a high performance dsp datapath

8-Channel Polyphase FIR Filter

8-Channel Polyphase FIR Filter

8-Channel Polyphase FIR Filter

8-Channel Polyphase FIR Filter

Complex Mixer + Adder

Complex Mixer + Adder

Complex Mixer + Adder

Complex Mixer + Adder

1024-point, Radix 4, Complex FFT

1024-point, Radix 4, Complex FFT

1024-point, Radix 4, Complex FFT

1024-point, Radix 4, Complex FFT

DSP Builder Advanced Blockset AdvantageBuilding a High-performance DSP Datapath

This Design Needs to Close Timing at 350 MHz.

Portion of a

High-end Radar

Front-end

Design

4 Instances


Dsp builder advanced blockset design flow build the design in matlab simulink

DSP Builder Advanced Blockset Design FlowBuild the Design in MATLAB/Simulink

High-level Simulink Design Description

Complex Mixer/Adder

FIR Filter

Complex FFT


Dsp builder advanced blockset design flow set the desired f max within simulink

DSP Builder Advanced Blockset Design FlowSet the Desired fMAX Within Simulink

Set fMAX Constraints Within the High-level Simulink Design Description


Evolution of the dsp block

36

36

36

36

36

36

36

36

Evolution of the DSP Block

Stratix II FPGA

Stratix III/IV FPGA

Stratix V FPGA

Variable-precision

DSP Block

DSP Block

72

64

32

72

DSP Half Block

Variable-precision

DSP Block

64

32

72

72

Variable-precision

DSP Block

72

64

32

72

DSP Half Block

Variable-precision

DSP Block

72

64

32

72

Eight 18x18 Multipliers (Sum)

Four 18x18 (Independent)

Eight 18x18 Multipliers (Sum)

Eight 18x18 (Independent)

High-precision Mode

Four 18x18 (Independent)

Highest Performance, Highest Precision DSP (28 nm)


The first variable precision dsp block

The First Variable-precision DSP Block

18-Bit Precision Mode

High-Precision Mode

First DSP Architecture with Two Native Precision Modes


Variable precision dsp block 18 bit precision mode

Configurable

X

+

_

64-bit

Acc

37

18

18

18

18

18

18

18

X

X

Sum Mode

18

Variable-precision DSP Block18-Bit Precision Mode

Backward-compatible

with Stratix III and Stratix IV FPGAs

X

32

32

Independent Mode


Variable precision dsp block high precision mode

Configurable

64

64

Acc

Reg

Acc

Reg

Variable-precision DSP BlockHigh-precision Mode

36 Bits

27 Bits

18x36

27x27

X

X

Input Register

Input Register

18 Bits

27 Bits

Competing 18x25 DSP Blocks are Limited to25-Bit Data Precision Only


Variable precision dsp block floating point precision

Configurable

27 Bits

64

64

Acc

Reg

Acc

Reg

27

27x27

27x27

X

X

co-eff

Input Register

Input Register

27 Bits

27 Bits

Variable-precision DSP BlockFloating-point Precision

FPGA Industry First!

Single-precision Floating-point Mantissa MultiplicationCan Be Implemented in One Variable-precision DSP Block


Variable precision with 64 bit cascade

Variable Precision with 64-Bit Cascade

64-Bit Accumulator

64-Bit Cascade Bus

64 Bits Allows for Cascading Without Loss in Precision


Variable precision with 64 bit cascade 18 bit precision mode

18

X

36 Bits

18

18

36 Bits

X

18

18

36 Bits

X

18

Variable Precision with 64-Bit Cascade 18-Bit Precision Mode

64-Bits

Three Competing 18x25 DSP BlocksWould Be Required to Do This


Ffts require high precision complex multiply

FFTs Require High-precision Complex Multiply

18x25 Precision

18x18 Precision

18x36 Precision

Data Width Increases with Each Stage;

Coefficient Width Stays the Same


Variable precision with 64 bit cascade efficient complex multiply

Variable Precision with 64-Bit Cascade Efficient Complex Multiply

18x18 Complex

18x25 Complex

Competing 18x25 DSP Requires:

18x36 Complex

4 Blocks

8 Blocks

4 Blocks


Variable precision with 64 bit cascade floating point precision

Variable Precision with 64-Bit CascadeFloating-point Precision

FPGA Industry First!

OR

Single-precision Mantissa Multiplication

27x27 Mode

Double-precision Mantissa Multiplication

54x54 Mode


Variable precision with 64 bit cascade single precision floating point fft

Variable Precision with 64-Bit CascadeSingle-precision Floating-point FFT

27x27 Complex Multiply

FPGA Industry First!

Eight Competing 18x25 DSP BlocksWould Be Required to Do This


Variable precision dsp advantage

Variable-precision DSP Advantage

Achieve Performance Goals Using Half the FPGA DSP Resources


Variable precision dsp advantage1

Variable-precision DSP Advantage

⅓ DSP

Resources

½ DSP

Resources

½ DSP

Resources

Fixed

Precision

Fixed

Precision

Fixed

Precision

Variable

Precision

Variable

Precision

Variable

Precision

Military Radar

Wireless Basestations

Video Processing


Variable precision dsp block

Variable-precision DSP Block

Internal Coeff.

Blocks

Hard Pre-adder


Variable precision dsp block hard pre adder for filters

D3

D2

D0

D1

+

+

C1

C0

X

X

+

Variable-precision DSP BlockHard Pre-adder for Filters

D3

D2

D1

D0

C0

C0

C1

C1

X

X

X

X

+

+

+

Pre-adder Reduces Multiplier Count by Half


Variable precision dsp block internal coefficient register banks

Variable-precision DSP BlockInternal Coefficient Register Banks

27 Bits

18 Bits

  • Dual, independent 18-bit or single 27-bit wide banks

  • Both are eight registers deep

  • Dynamic, independent register addressing

  • Eases timing closure and eliminates external registers

0

0

1

1

2

2

3

3

OR

4

4

5

5

6

6

7

7


Summary competitive

Summary: Competitive


For more information

For More Information

  • Download our DSP architecture whitepaper

    • FPGA Industry’s first variable precision DSP architecture

  • Download the Stratix V FPGA handbook


Thank you for more information visit www altera com

Thank You!For more information visit: www.altera.com


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