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Pixel hybride 3 d en techno 0 13 m pour slhc atlas

Pixel Hybride 3-D en techno 0.13µm pour SLHC/ATLAS

S. Godiot a, M. Barbero b, B. Chantepie a, J.C. Clémens a, R. Fei a, J. Fleury c, D. Fougeron a, M. Garcia-Sciveres c, T. Hemperek b, M. Karagounis b, H. Krueger b, A. Mekkaoui c, P. Pangauda, A. Rozanov a, N. Wermes b

a Centre de Physique des Particules de Marseille, France

b University of Bonn, Germany

c Lawrence Berkeley National Laboratory, California, USA


Outline
Outline

  • Pixel pour Atlas/LHC

  • Projet SLHC

  • Version 3D

  • MPW TERRAZON/CHARTERED


Pixels pour upgrade de atlas lhc

Config word=12b

4 bits

5 bits

CC/CF2=5.8

CF=17fF

Pixels pour upgrade de Atlas/LHC

Constraints

Noise under 100e-

Threshold around 1000e-

Dispersion threshold 200e-


Fe i4 fe tc4 analog preamplifier

Leakage Comp. Transistor

Local Feedback tuning 4b

Feedback structure

Core Preamp

Injection switches and caps

FE-I4/FE-TC4 : Analog Preamplifier


Hybrid pixels detector for hep atlas lhc example

50 μm

FE-I3 CMOS technology : 250 nm

Done : ATLAS/LHC

(2008/2009)

Under Design

ATLAS/LHC upgrade project

(2014…)

50 μm

400 μm

FE-I4 CMOS technology : 130 nm

250 μm

Hybrid Pixels detector for HEP (Atlas/LHC example)

And silicon sensor with the same pixel dimension


3 d hybrid pixels detector atlas slhc example

Done : ATLAS/LHC

2008/2009

Under Design

ATLAS/LHC

upgrade project

(2014…)

FE-I3 CMOS technology : 250 nm

50 μm

400 μm

50 μm

FE-I4 CMOS technology : 130 nm

250 μm

Drastic pixel dimension reduction (cost effective compared to smallest technologies ?)

Why not ??

ATLAS/SLHC

(10 years after LHC..)

50 μm

125 μm

New mechanical possibilities

50 μm

Dream,dream,dream ???

ATLAS/SLHC

100 μm

3-D Hybrid Pixels detector (Atlas/SLHC example)


Pixel 3 d

Config word=12b

4 bits

5 bits

CC/CF2=5.8

CF=17fF

Pixel -> 3-D

FE-TC4-EA :

2 possible ways for discriminator output read-out:

  • With the simple read-out part existing yet into the pixel

  • With the tier 2 (via the Bond Interface)

FE-TC4-DS :

dedicated for

parasitic coupling studies

between the 2 tiers.

FE-TC4-DC :

Read-out chip similar to what is foreseen for FE-I4


Fe i4 to fe tc4
FE-I4 to FE-TC4

FEI4 : IBM 0.13µ

1P8M LV

FEI4 : CHARTERED 0.13µ

1P5M LP

  • Bond Interface

  • 5µm step

  • TSV

  • 1.5µ diameter


sensor

Back Side Metal

SuperContact

Tier 1

(thinned wafer)

M1

M2

M3

M4

M5

Bond Interface

M6

M6

M5

M4

M3

M2

M1

Tier 2

SuperContact

2d Tiers -> Simple : Counter + parasitic coupling studies -> Complex :Read-out chip similar to what is foreseen for FE-I4


Fermilab 3 d multi project run
Fermilab 3-D Multi-Project Run

  • Fermilab has planned a dedicated 3-D multi project run using Tezzaron for HEP during 2009

  • There are 2 layers of electronics fabricated in the Chartered 0.13 um process, using only one set of masks. (Useful reticule size 15.5 x 26 mm)

  • The wafers are bonded face to face.

ATLAS/SLHC

Sub-part


Fermilab 3 d multi project run the atlas slhc prototype with 2 tiers

SEU-3D

SEU-3D

FETC4-AE

FETC4-DSDC

TSV Daisy Chain + BI

TSV vs Transistors

Mechanical stress

DFF + Tr + Cap

TSV vs Transistors

+ capacitors

Fermilab 3-D Multi-Project Run The Atlas/SLHC prototype with 2 tiers

SENSOR


Fec4 first results of first chip in chartered 0 13lp 1p8m
FEC4 -> First results of first chip in Chartered 0.13LP 1P8M

  • Due to schedule no optimization of transistors has been done

  • Main results are equivalent to IBM ones.

    • Threshold min around 1100 e-

    • Un-tuned threshold dispersion 200 e-

    • Noise lower than 80 e-

  • Problem discovered after 160 MRad on latches ( output tends to be blocked in "1" state)

    • Difficult to work with the circuit by

    • after

    • Problem reproduced in simulation

    • "corners" (SF and FS case)

    • … but

    • Analog is still working even with

    • increased of noise : 250 e- (threshold

    • dispersion is meaningless)


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