slide1
Download
Skip this Video
Download Presentation
Overall Project Objective:

Loading in 2 Seconds...

play fullscreen
1 / 12

Overall Project Objective: - PowerPoint PPT Presentation


  • 74 Views
  • Uploaded on

Overall Project Objective: Design a Radio-Frequency indoor/outdoor navigation system, utilizing the existing wireless infrastructure. Design Stage Objective: Final LVS and simulation.

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about ' Overall Project Objective:' - jeff


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
slide1

Overall Project Objective:

Design a Radio-Frequency indoor/outdoor navigation system, utilizing the existing wireless infrastructure.

Design Stage Objective:

Final LVS and simulation

RF Triangulator: Indoor/Outdoor Location Finding18-525 Architecture ProposalGiovanni FonsecaDavid FuAmir GhitiStephen RoosDesign Manager: Myron Kwai

status
Status

Structural Verilog complete.

Schematics completed.

Layout of basic components complete.

Major Layouts:

~90% done

FPU: Done, tested.

Lookup: Done, tested.

Calc: interconnects.

Top Three: Finishing layout: 85% done

Global routing still needs to be done

slide3

Current Transistor counts

  • Total: 27,150 transistors*
  • Top Three: 6,500 trans.

3 x FPU Add/Sub Unit 1500 trans.

Control Registers & Muxes: 2000 trans.

  • Calc: 17,950 trans.

2 x FPU Add/Sub Unit: 1500 trans.

1 x FPU Mult/Div Unit: ~5000 trans.

1 x Logshifter: 200 trans.

1 x Comparator: 800 transistors.

FSM Logic: 850 transistors

25 x 12-bit M-S En Reg: 6600 trans. total

8-1,6-1,4-1,2-1 Mux Sets: 3000 trans. total

  • Lookup: 2,700 trans.

Control Registers & Muxes: 2000 trans.

Control Logic: 163 trans.

    • SRAM: 12k trans

* count not including SRAM, with SRAM: ~38k

fpu layouts
FPU Layouts

Multiplication & Division Layout

FASU Layout

lookup layout
Lookup Layout

Total transistor count:

15018 in layout

14851 in schematic

Area = 208.8*232.3

= 48504u^2.

Density:

.31 transistor per u^2.

top three progress
Top Three Progress

Last week’s

This week’s

to do
To do
  • Lookup: done
  • FPU: done
  • Calc:
    • Finish up the interconnects.
  • Top Three:
    • Finish up the interconnects.
    • Split the schematics and layout into parts for LVS
questions concerns
Questions/Concerns
  • Large block simulations take a long time
  • Getting top3 and calc to lvs before carnival!
ad