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Chapter 6. Functions of Combinational Logic. Adder. Figure 6--1 Logic symbol for a half-adder. Figure 6--2 Half-adder logic diagram. Figure 6--3 Logic symbol for a full-adder. Figure 6--4 Full-adder logic. Figure 6--5 Full-adder implemented with half-adders.

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Chapter 6 l.jpg

Chapter 6

Functions of Combinational Logic


Figure 6 1 logic symbol for a half adder l.jpg

Adder

Figure 6--1 Logic symbol for a half-adder


Figure 6 2 half adder logic diagram l.jpg
Figure 6--2 Half-adder logic diagram.


Figure 6 3 logic symbol for a full adder l.jpg
Figure 6--3 Logic symbol for a full-adder


Figure 6 4 full adder logic l.jpg
Figure 6--4 Full-adder logic


Figure 6 5 full adder implemented with half adders l.jpg
Figure 6--5 Full-adder implemented with half-adders.


Figure 6 7 block diagram of a basic 2 bit parallel adder using two full adders l.jpg
Figure 6--7 Block diagram of a basic 2-bit parallel adder using two full-adders.


Figure 6 9 a 4 bit parallel adder l.jpg
Figure 6--9 A 4-bit parallel adder.


Figure 6 10 four bit parallel adders l.jpg
Figure 6--10 Four-bit parallel adders.


Figure 6 12 examples of adder expansion l.jpg
Figure 6--12 Examples of adder expansion.


Figure 6 13 two 74ls83a adders connected as an 8 bit parallel adder pin numbers are in parentheses l.jpg
Figure 6--13 Two 74LS83A adders connected as an 8-bit parallel adder (pin numbers are in parentheses).


Figure 6 14 a voting system using full adders and parallel binary adders l.jpg
Figure 6--14 A voting system using full-adders and parallel binary adders.


Figure 6 15 basic comparator operation equality l.jpg
Figure 6--15 Basic comparator operation. (Equality)

Comparators


Figure 6 16 logic diagram for equality comparison of two 2 bit numbers l.jpg
Figure 6--16 Logic diagram for equality comparison of two 2-bit numbers



Figure 6 18 logic symbol for a 4 bit comparator with inequality indication l.jpg
Figure 6--18 Logic symbol for a 4-bit comparator with inequality indication.



Slide20 l.jpg
Figure 6--20 Pin diagram and logic symbol for the 74HC85 4-bit magnitude comparator (pin numbers are in parentheses).


Figure 6 21 an 8 bit magnitude comparator using two 74hc85s l.jpg
Figure 6--21 An 8-bit magnitude comparator using two 74HC85s.


Figure 6 22 decoding logic for the binary code 1001 with an active high output l.jpg
Figure 6--22 Decoding logic for the binary code 1001 with an active-HIGH output.

Decoders


Figure 6 23 decoding logic for producing a high output when 1011 is on the inputs l.jpg
Figure 6--23 Decoding logic for producing a HIGH output when 1011 is on the inputs.


Figure 6 24 logic symbol for a 4 line to 16 line 1 of 16 decoder l.jpg
Figure 6--24 Logic symbol for a 4-line-to-16-line (1-of-16) decoder.


Figure 6 28 the 74hc42 bcd to decimal decoder l.jpg

BCD-to-Decimal Decoder

Figure 6--28 The 74HC42 BCD-to-decimal decoder.



Figure 6 30 logic symbol for a bcd to 7 segment decoder driver with active low outputs l.jpg

BCD-to-7-Segment Decoder

Figure 6--30 Logic symbol for a BCD-to-7-segment decoder/driver with active-LOW outputs.


Figure 6 31 pin diagram and logic symbol for the 74ls47 bcd to 7 segment decoder driver l.jpg
Figure 6--31 Pin diagram and logic symbol for the 74LS47 BCD-to-7-segment decoder/driver.


Figure 6 32 examples of zero suppression using the 74ls47 bcd to 7 segment decoder driver l.jpg
Figure 6--32 Examples of zero suppression using the 74LS47 BCD to 7-segment decoder/driver.


Figure 6 33 logic symbol for a decimal to bcd encoder l.jpg

Encoders

Figure 6--33 Logic symbol for a decimal-to-BCD encoder.


Slide33 l.jpg

Figure 6--34 Basic logic diagram of a decimal-to-BCD encoder. A 0-digit input is not needed because the BCD outputs are all LOW when there are no HIGH inputs.


Slide34 l.jpg

Figure 6--35 Pin diagram and logic symbol for the 74HC147 decimal-to-BCD priority encoder (HPRI means highest value input has priority).


Figure 6 36 logic symbol for the 74f148 8 line to 3 line encoder l.jpg
Figure 6--36 Logic symbol for the 74F148 8-line-to-3-line encoder.


Figure 6 37 a 16 line to 4 line encoder using 74f148s and external logic l.jpg
Figure 6--37 A 16-line-to-4 line encoder using 74F148s and external logic.


Figure 6 38 a simplified keyboard encoder l.jpg
Figure 6--38 A simplified keyboard encoder.


Slide38 l.jpg

Code Converter

BCD-to-Binary Conversion


Figure 6 39 four bit binary to gray conversion logic l.jpg
Figure 6--39 Four-bit binary-to-Gray conversion logic.


Figure 6 40 four bit gray to binary conversion logic l.jpg
Figure 6--40 Four-bit Gray-to-binary conversion logic


Figure 6 41 example 6 13 l.jpg
Figure 6--41 : Example 6-13


Figure 6 42 logic symbol for a 1 of 4 data selector multiplexer l.jpg

Multiplexers (Data Selectors)

Figure 6--42 Logic symbol for a 1-of-4 data selector/multiplexer.


Figure 6 43 logic diagram for a 4 input multiplexer l.jpg
Figure 6--43 Logic diagram for a 4-input multiplexer.



Slide46 l.jpg
Figure 6--45 Pin diagram and logic symbol for the 74HC157A quadruple 2-input data selector/multiplexer.


Figure 6 46 pin diagram and logic symbol for the 74ls151 8 input data selector multiplexer l.jpg
Figure 6--46 Pin diagram and logic symbol for the 74LS151 8-input data selector/multiplexer.


Figure 6 47 a 16 input multiplexer l.jpg
Figure 6--47 A 16-input multiplexer.


Figure 6 48 simplified 7 segment display multiplexing logic l.jpg
Figure 6--48 Simplified 7-segment display multiplexing logic.


Figure 6 51 a 1 line to 4 line demultiplexer l.jpg

Demultiplexers

Figure 6--51 A 1-line-to-4-line demultiplexer.



Figure 6 53 the 74hc154 decoder used as a demultiplexer l.jpg
Figure 6--53 The 74HC154 decoder used as a demultiplexer.



Figure 6 55 the 74ls280 9 bit parity generator checker l.jpg
Figure 6--55 The 74LS280 9-bit parity generator/checker.


Figure 6 61 typical configuration for conventional pld programming l.jpg

Programmable Logic

Figure 6--61 Typical configuration for conventional PLD programming.


Figure 6 62 flow chart of an spld conventional programming sequence l.jpg
Figure 6--62 Flow chart of an SPLD conventional programming sequence.


Figure 6 63 typical configuration for in system programming of a pld l.jpg
Figure 6--63 Typical configuration for in-system programming of a PLD.


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