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Technion – Israel Institute of Technology Department of Electrical Engineering High Speed Digital Systems Lab. Spring 2007. Fast Communication for Multi – Core SOPC. Supervisor: Evgeny Fiksman Performed by: Moshe Bino Alex Tikh. Table of Contents. General.

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fast communication for multi core sopc

Technion – Israel Institute of Technology

Department of Electrical Engineering

High Speed Digital Systems Lab

Spring 2007

Fast Communication for Multi – Core SOPC

Supervisor: Evgeny Fiksman

Performed by:

Moshe Bino

Alex Tikh

general
General
  • Programmable hardware chips present a wide base for developing SOPC systems.
  • SOPC systems include generic soft-core processor called Microblaze and basic programmable elements.
  • MPI – Message Passing Interface enable working with fast communication.
project goals
Project goals
  • Implementation of mini distributed core system using MPI router .
  • Build an infrastructure for fast communication in multi-core system.
  • Build a designated C/C++ application to show the advantages of working with parallel system.
software
Software

Development environment

  • Embedded Development Kit (EDK) is a suite of tools and IP* that enables to design a complete embedded processor system.
  • Integrated Software Environment (ISE) - software development tools that allow to circumvent some of designing complexity.

* IP = Intellectual property

hardware
Hardware

Development environment

  • The Virtex-II Pro FPGA contain platform for designs that are based on IP cores and customized modules.
  • The MicroBlaze core is a 32-bit RISC* Harvard architecture soft processor core with 32 general purpose registers, ALU, and a rich instruction set optimized for embedded applications.

*RISC = Register Instruction Set Computer

hardware1
Hardware

Configuration

  • The top design will include 4 MicroBlaze processors connected by direct point to point Fast Simplex Links (FSLs) for interprocessor communication.
  • FSL Bus is a uni-directional point-to-point communication channel bus used to perform fast communication between any two design elements on the FPGA when implementing an interface to the FSL bus.
hardware2
Hardware

Kit used – XUP Virtex - II Pro Board

test debbug
Test & Debbug

Unit test

  • ModelSim is a simulation and debug environment, combining high performance with powerful and intuitive GUI.
  • ChipScope Pro inserts logic analyzer, bus analyzer, and Virtual I/O low-profile software cores directly into your design, allowing to view any internal signal or node, including embedded hard or soft processors.
test debug
Test & Debug

Chip scope pro system block diagram

test debbug1
Test & Debbug

System test

  • Run a test application - create small application and look for expected results. If expectations are not met, debug with Xilinx Microprocessor Debugger tool (XMD) which is a software debugger for a multi-processor system.
time table second semester
Time Table – second semester
  • Build a quad core system
  • Implementing router for 4 processors
  • Test and debug
  • Run a test application
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